Completed custom digital layout of memory peripherals such as sensamp, row decode, column mux and custom IO in 7nm FinFet TSMC technology. Also, manual place and route of standard cell clocking and control logic. First three months of contract were on site in Raleigh, NC. Remainder was working with the Raleigh team but remote from the Austin office (w/o supervision). All work was completed on time or ahead of schedule. Used Cadence VXL and Calibre verifications.

Helped finish up conversion of a SOI14 design to 14HP. Completed two digital 14nm FinFet memory macros to all PDV checks. Also worked on completing Memory Compiler macros. Used Cadence VXL, Calibre, and in house tools and checking decks.

Worked directly with the circuit design engineer to complete multiple passes of a complex SRAM macro from conception to top level complete at 5ghz. Layouts used the TSMC 20nm process technology which included correcting G0 dual metal pattern violations, resolving OD.S.13 issues for better device integrity, low power improvements, and antenna diodes. Utilized Cadence VXL layout software and Calibre verification software.

Worked on leading edge technologies (down to 22nm) on multiple projects and macros. Was part of a small team, working cross-site on a Memory Compiler project used in Fusion technology. We completed three independent generations of memory compilers, each ahead of schedule, while remaining flexible to changes in logic and technology. Worked closely with engineers to optimize designs, reduce power issues, address DFM concerns and maintain flexibility.

Contracted at Motorola/freescale - In CMOS090gp (7 metal 2 thick) process, I worked on I/O analog, digital, and sstl pad designs for Omega 90nm test chip as well as some library development. In CMOS090gpf process, I worked on some high voltage test structures. In Hip7a and Hip7af processes, I worked on I/O pads and analog macro blocks such as VREG and PLL for Copperhead.

Contracted at Motorola - Worked on three projects and multiple processes. 1) Power reduction project. - modified and rearranged existing block as well as created new layout. 2) Flash memory hardblock - transferred layout from remote libraries and updated to match schematics. Worked on probe pad circuitry layout that included ESD protection and unique metal routing. 3) Embedded memory blocks - leaf cell generation and sub-block layout.

Hired as “temporary” in October to assemble digital padring in TSMC .18 process and do process migration of pads from TSMC .18 to TSMC .15 and from TSMC .15 to TSMC .13 process. Became a permanent employee in January 2002. Worked mostly on digital and analog pads. Assembled custom analog and high speed circuits for blocks such as SerDes, Regulator, and Reference in TSMC .18, .15, and .13 and CSM .13 processes.

04/01 - 06/01 Motorola / C-Port - Process migration using TSMC .15 process.02/01 - 03/01 Cirrus Logic - DRC and LVS edits with some custom layout on a computer audio chip using TSMC .35 process. 12/00 - 02/01 Motorola - Custom digital and analog circuit layout using Hip7 process. Worked on Bluetooth analog block. Floorplanned small blocks.09/00 - 12/00 Cicada Semiconductor - Custom analog circuit layout using TSMC .18 process and Calibre. Worked on Quad port Gigabit Ethernet PHY high-speed chip.07/00 - 09/00 Sigmatel - Custom digital circuit layout for datapath block using Sig25 .25 process.