Formal verification engineer on the debug and trace unit on a coherent mesh network.

• Verified the Instruction Fetch Unit (IFU) low power A-class processor.• Bring up of top level MMU formal flow fixing 4 independent counter examples to increase verification confidence in design.• Update architecture model and pipeline follower responding to MMU design changes.• Diagnose, debug, and fix over 16 independent formal counter examples in the IFU bringing up 12 separate SEC, Liveness, XPROP, and FPV formal flows providing more verification confidence and design feedback. • Create abstractions to bring out more formal counter examples, and to increase design confidence.• Implemented Statistical coverage for the IFU using Eventdb, Ruby, and SystemVerilog.• Enable directed tests for the IFU by altering the Universal Verification Methodology (UVM) test bench.

Developed course material, graded,and held office hours and recitations for Logic Design and Verification, and Computer Architectures courses.

Optimized a digital mixed signal model using Cadence Stratus High Level Synthesis (HLS). Achieved an 237% emulation frequency increase with only an 6% increase in area for designs compiled in Cadence Palladium.

Verified liveness of the M85 processor memory system using JasperGold.

Designed and wrote code in MATLAB to model the spread of COVID-19 in Pittsburgh, PA, and the effects of different containment policies.

Improved testing software using C# and Python.