Christopher Hess Email & Phone Number

San Francisco Bay Area

• Responsible for Yield & Performance Characterization including the characterization of failure modes and variability of integrated circuits to drive processing improvements as well as design for manufacturability.
• Design of hundreds of test chips for the microelectronics industry over numerous technologies including Bulk, (FD) SOI, FIN and GAA device as well as front and backside wafer routing
• Development of a “lego” based approach to design and layout of test chips to reduce overall design time and to enable porting layout across multiple technology nodes and or design styles
• Development of interleaved probing techniques to double the pad count within a given chip area
• Development of three-dimensional floor planning and place and route (P&R) of experiments to boost area efficiency
• Development of three-dimensional stackable test chip shuttles to reduce mask cost

Karlsruhe Area, Germany

• Founding Member of the Defect Diagnosis Group at the Institute of Computer Design and Fault Tolerance of the University of Karlsruhe.
• Development of novel methods for efficient in-line defect diagnosis by manufacturing and measuring test chips.
• Development of novel algorithms and software systems to analyze the measured data providing in-line process control information about different types of defects and statistical data on defects.