Christopher Ian Ignacio Email & Phone Number

Redmond, Washington, Us

Santa Clara, California, Us

Client and SOC System test Product Development: Haswell Broadwell, Skylake, Kaby Lake, Coffee Lake, Comet Lake, Tiger Lake, and next generation Intel client products. Covers definition and test pathfinding for system level manufacturing socket; test program development, system integration and debug; and deployment to high volume manufacturing.

Santa Clara, California, Us

- High Speed Serial IO product development for 14nm SOC- Technical individual contributor for Bench Design Validation (BDV) which charter establishing the infrastructure, and tools development to enable faster System Validation to ATE test correlation on HSIO Hard IPs. Utilizing DV Boards, Mixed Signal scopes, and BER Tools.- Data Eye Characterization for High Speed Serial IO on SOC (PCIE/USB3/SATA) using varying channel lengths of ISI (Inter Symbol Interference) test board.

Santa Clara, California, Us

- Worked with a team that developed and deployed production quality test programs for Haswell Microprocessor families ranging from Mobile, Desktop, Uni-Server and Convertible products- Performed system debug and analysis with Silicon Validation to narrow down performance failures on the CPU’s subsystem such as PCIE, cache controller, system agent, power controller unit and graphics subsystem. And on Multi-Chip Package (Haswell ULT) variants which incorporates legacy PCH Chipset: SATA, LAN and USB- Debug on firmware and BIOS issues to sustain and improve overall platform health- Test Hole debug, failure analysis for DPM improvement

Santa Clara, California, Us

- Engaged with Validation and Design in defining effective coverage on SOC subsystems and product features to ensure high quality samples and revenue parts shipment while also aiming to effectively Screen ATE coverage holes up front.- Designed the test framework for content execution on the SOC subsystem using commercial operating systems expected to run on this product. Laid out the automated test program architecture for high volume manufacturing.- Silicon Power On, debug, and test characterization

Santa Clara, California, Us

- Defined and developed system level test methods for the x58/5500/5520 chipset for High Volume Manufacturing (HVM) and functional testing- Developed and deployed HVM test programs for this next generation server chipset- Implemented a cost effective way of testing multiple server chipset variants on a single platform using available DFT features both on-board and Chipset.- Test Program development and deployment- Failure analysis and debug on system- DFT based Built-In Self Test (BIST) content correlation between Class tester and System by capturing test sequences from ATE and directly porting it to system.

Santa Clara, California, Us

- Debugged enterprise server and workstation chipsets 5000P/V/Z/X at system level, to identify ATE coverage holes and achieve the acceptable out going DPM quality metric with use of protocol and logic analyzers- Resolved POST HANG, PCIE Link Training Failures and Memory Read-Write Failure Signatures, USB and SATA burst failures.- Coded JTAG scripts for debugging the high speed IOs such as DDR2/3, PCIE, USB2, SATA1/2 and Front Side Bus- Captured logic and protocol analyzer traces of the minimum system bus transaction that modulates the failing signature and feed that back to design engineering

Santa Clara, California, Us

- Developed and delivered multiple test programs for E7520/E7525 chipset products for High Volume Manufacturing, including deployment for Multi-Socket server test system in the factory.- Debugged and closed a critical voltage margining fallout on the Front Side Bus to sustain acceptable DPM indicator