Developed test procedures for packeted-based timing and synchronization device based on engineering functional specificationsWrote system functional tests using scripts python and teraterm to test firmware upgrade, default configurations, and parameter changes.Created python script to confirm clock progressed through all possible stages.Learned to valid precision time protocol using wireshark and packet creating tool such as IXIA

Created Verification test plan for logic controller based on specification and RTL review.Generated test cases using UVM system verilog or custom verilog test benchSimulated test cases using QuestaSim 10.2 through SGE regressions and in GUI for test case debug. Resolved bugs by filing reports in bugzilla and speaking with design team to close the issue.Upgraded test case to confirm that original bug was fixedCreated coverage groups, cross coverage, and assertions based on design speciation using system verilogAnalyzed code coverage, prepared reports, and reported finding to team members using QuestaSim tools and ExcelUpdated test cases based on report to increase code coverage to 100%

Graded lap reports, supervised Lab section of the class, and helped students complete lab assignments.