Technical lead manager of ASIC physical design and implementation.

* Managed a team of physical design engineers to design and implement the next generation (10nm and beyond) Server Memory Controllers for Xeon®/Xeon Phi® Server CPUs.* Technically involved in floorplanning and integration execution.* Managed a small team of engineers to implement the UPI subsystem on the Skylake Server CPU. (14nm). Utilized MIM and MLPH techniques to maximize reuse and minimize effort.

* Took over the management of parts of the physical design organization for implementing Sandy Bridge Server steppings and additional SKUs. * Continued with technical responsibilities from previous role. Started training individual contributors to offload the technical work.* Started to build the team with both RCG and experienced hires for the expanding needs of the division.

* Completed multiple tape ins on Xeon chipsets.* 63xx IO Controller Hub: Created and led a team to develop local physical design expertise and bring this capability to a new organization. Executed under remote management with a lot of autonomy. Owned RTL->GDSII implementation of a sub-chip through tape in. This project was spread across 3 geographies adding to the organizational complexity.* X58 (Tylersburg): Contributed to the definition of a new product serving as the physical design expert responsible for the physical feasibility of the product (die size, cost, head count and schedule planning, etc). Stayed on the project through tape in as a physical design lead and full chip floorplan/integration owner. Coordinated with sub-team in India to implement some partitions in this design.* Sandy Bridge Server CPU: Transitioned to the Intel CPU group and brought ASIC design methodologies to the CPU uncore to implement the PCIE and UPI (Intel's off chip coherency interface). Primarily responsible for floorplanning and integration. Also contributed to tools, flow, and methodology development to bring new capabilities to Intel's traditional custom design methodologies.

* Technical responsibilities included full chip floorplanning, global clock design, die size optimization, package interface, and integration.* As the Tech Lead, organized and drove execution of the Structural Design Team.* Utilized proprietary as well as industry standard tools.

SuperDome high-end Server * Post Si electrical validation, characterization, and debug across many subsystems including high speed differential links, memory subsystem, backplane/cross bar, and power subsystem. * Multiple board designs including a stand alone scan tester for all 5 chipset ASICs and a custom hardware+software boot emulator allowing the testing of boot time firmware and the IO subsystem before the coherency controller chip+CPU were available * Built a custom "inside out prototype" for easier electrical debug. Nicknamed, "Frankenstein", this system supported a fully capable, single cell SuperDome outside of its cabinet. This required mechanical design, custom cooling solution, a custom power subsystem, and software overrides to defeat and bypass the required sensors, controls, etc * Contributed to the developed of post-Si prototype planning (budgeting, ordering, space planning, satisfying testing requirements, etc)

* Primary project involved writing a windows based GUI interface for a classified military communications device for the field teams to configure and, if needed, debug the system. * The interface was written in C++ and utilized compiled libraries to increase security for memory addresses and register definitions. * This device was the heart of the communications system in the J-STARs platform.