Christopher Tracy

Christopher Tracy Email and Phone Number

ASIC Frontend Design and/or Verification @
Christopher Tracy's Location
Santa Barbara, California, United States, United States
About Christopher Tracy

Over 30 years of experience in the electronics industry. My early career years were spent doing ASIC/FPGA design at multiple companies, while in the most recent years I have been doing systems engineering at an aerospace infrared (IR) camera company. The ASIC/FPGA work provided me experience in all aspects of front-end design: architecture development, RTL design, testbench development, validation, synthesis, static timing analysis, power analysis, processor microcode development and built-in self test (BIST). The systems engineering work provided me experience in a variety of IR detector technologies, writing requirements specifications (HW, FW, SW) and leading multi-disciplined engineering teams.

Christopher Tracy's Current Company Details
Self-employed

Self-Employed

ASIC Frontend Design and/or Verification
Christopher Tracy Work Experience Details
  • Self-Employed
    Asic Design And/Or Verification Engineer
    Self-Employed Sep 2022 - Present
    California, United States
    I am currently looking for work doing ASIC frontend design and/or verification. The early part of my career was spent doing this type of work while more recently I have been doing systems engineering. In order to be more current in my ASIC related job skills I have been learning SystemVerilog, UVM, Python.
  • Raytheon Vision Systems
    Principal Systems Engineer / Senior Principal Systems Engineer
    Raytheon Vision Systems Dec 2003 - Aug 2022
    California, United States
    Technical lead on various programs where responsibilities included: • Requirements and design specification development. • Requirements flow down to all of the engineering disciplines involved – detector, integrated circuit, electronics, FW, SW, mechanical and test. • Coordinating with non-engineering groups (e.g., manufacturing, supply chain management) to ensure that both program technical and schedule requirements were met. • Analysis of program test data for the purpose of identifying sources of adverse yield trends.
  • Sanbar Networks
    Lead Asic Engineer
    Sanbar Networks Feb 2002 - Nov 2003
    California, United States
    Co-founded a fabless semiconductor company whose SoC product, a 12Gbps storage protocol processor, targeted the enterprise class storage market. Shared responsibility for market surveys, product identification, soliciting customer requirements and partitioning the design between HW and embedded SW. Solely responsible for defining major sub-block, a 12Gbps TCP/IP offload engine (TOE). Developed the TOE’s requirements specification, defined its macro architecture and developed its high-level design specification.
  • Tality / Cadence Design Systems
    Senior Design Engineer / Senior Design Services Manager
    Tality / Cadence Design Systems Sep 1997 - Jan 2002
    California, United States
    Responsibilities included engineering management, new business development, customer technical interface, authoring design specifications, defining testbench architectures, developing chip-level test plans, performing chip-level static timing analysis and doing block-level RTL design.
  • Cisco / Stratacom
    Hardware Engineer
    Cisco / Stratacom May 1996 - Aug 1997
    California, United States
    Member of a design team that developed a bus interface unit integrated circuit. This device had built-in ATM pacing and SAR support, and had interfaces to a 68360 processor, a SPARClite processor and a PCI PHY. Responsibilities included chip-level synthesis, chip-level static timing analysis, floor planning, pad assignments, bond editing and release simulation vectors. Was also responsible for check out of the first batch of development boards containing the prototype ASIC.
  • Delco Electronics
    Digital Design Engineer
    Delco Electronics Jan 1991 - Jan 1996
    California, United States
    Member of a design team that developed a micro-programmable avionics bus interface ASIC. Designed and implemented multiple asynchronous FIFOs and built in self-test (BIST) blocks. Wrote BIST microcode for the register file block, which was comprised of embedded dual ported RAMs and registers. Lead engineer responsible for developing system level models used for functional, chip-level validation and throughput bench marking of the ASIC.

Christopher Tracy Education Details

  • University Of California Santa Barbara
    University Of California Santa Barbara
    Gpa 3.7 Out Of 4.0
  • University Of California, Santa Barbara
    University Of California, Santa Barbara
    Gpa 3.6 Out Of 4.0

Frequently Asked Questions about Christopher Tracy

What company does Christopher Tracy work for?

Christopher Tracy works for Self-Employed

What is Christopher Tracy's role at the current company?

Christopher Tracy's current role is ASIC Frontend Design and/or Verification.

What schools did Christopher Tracy attend?

Christopher Tracy attended University Of California Santa Barbara, University Of California, Santa Barbara.

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