Christopher Tracy
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Christopher Tracy Email & Phone Number

ASIC Frontend Design and/or Verification at Self-employed
Location: Santa Barbara, California, United States 6 work roles 2 schools
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Current company
Self-employed
Role
ASIC Frontend Design and/or Verification
Location
Santa Barbara, California, United States

Who is Christopher Tracy? Overview

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Christopher Tracy is listed as ASIC Frontend Design and/or Verification at Self-employed, based in Santa Barbara, California, United States. AeroLeads shows a matched LinkedIn profile for Christopher Tracy.

Christopher Tracy previously worked as ASIC Design and/or Verification Engineer at Self-Employed and Principal Systems Engineer / Senior Principal Systems Engineer at Raytheon Vision Systems. Christopher Tracy holds Master Of Engineering - Meng, Computer Engineering, Gpa 3.7 Out Of 4.0 from University Of California Santa Barbara.

Profile bio

About Christopher Tracy

Over 30 years of experience in the electronics industry. My early career years were spent doing ASIC/FPGA design at multiple companies, while in the most recent years I have been doing systems engineering at an aerospace infrared (IR) camera company. The ASIC/FPGA work provided me experience in all aspects of front-end design: architecture development, RTL design, testbench development, validation, synthesis, static timing analysis, power analysis, processor microcode development and built-in self test (BIST). The systems engineering work provided me experience in a variety of IR detector technologies, writing requirements specifications (HW, FW, SW) and leading multi-disciplined engineering teams.

Current workplace

Christopher Tracy's current company

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Self-employed
Self-Employed
ASIC Frontend Design and/or Verification
6 roles

Christopher Tracy work experience

A career timeline built from the work history available for this profile.

Asic Design And/Or Verification Engineer

Current
Self-Employed

California, United States

I am currently looking for work doing ASIC frontend design and/or verification. The early part of my career was spent doing this type of work while more recently I have been doing systems engineering. In order to be more current in my ASIC related job skills I have been learning SystemVerilog, UVM, Python.

Sep 2022 - Present

Principal Systems Engineer / Senior Principal Systems Engineer

Raytheon Vision Systems

California, United States

  • Technical lead on various programs where responsibilities included:
  • Requirements and design specification development.
  • Requirements flow down to all of the engineering disciplines involved – detector, integrated circuit, electronics, FW, SW, mechanical and test.
  • Coordinating with non-engineering groups (e.g., manufacturing, supply chain management) to ensure that both program technical and schedule requirements were met.
  • Analysis of program test data for the purpose of identifying sources of adverse yield trends.
Dec 2003 - Aug 2022

Lead Asic Engineer

Sanbar Networks

California, United States

Co-founded a fabless semiconductor company whose SoC product, a 12Gbps storage protocol processor, targeted the enterprise class storage market. Shared responsibility for market surveys, product identification, soliciting customer requirements and partitioning the design between HW and embedded SW. Solely responsible for defining major sub-block, a 12Gbps.

Feb 2002 - Nov 2003

Senior Design Engineer / Senior Design Services Manager

Tality / Cadence Design Systems

California, United States

Responsibilities included engineering management, new business development, customer technical interface, authoring design specifications, defining testbench architectures, developing chip-level test plans, performing chip-level static timing analysis and doing block-level RTL design.

Sep 1997 - Jan 2002

Hardware Engineer

Cisco / Stratacom

California, United States

Member of a design team that developed a bus interface unit integrated circuit. This device had built-in ATM pacing and SAR support, and had interfaces to a 68360 processor, a SPARClite processor and a PCI PHY. Responsibilities included chip-level synthesis, chip-level static timing analysis, floor planning, pad assignments, bond editing and release.

May 1996 - Aug 1997

Digital Design Engineer

Delco Electronics

California, United States

Member of a design team that developed a micro-programmable avionics bus interface ASIC. Designed and implemented multiple asynchronous FIFOs and built in self-test (BIST) blocks. Wrote BIST microcode for the register file block, which was comprised of embedded dual ported RAMs and registers. Lead engineer responsible for developing system level models.

Jan 1991 - Jan 1996
2 education records

Christopher Tracy education

Master Of Engineering - Meng, Computer Engineering, Gpa 3.7 Out Of 4.0

University Of California Santa Barbara

Bachelor Of Engineering - Be, Computer Engineering, Gpa 3.6 Out Of 4.0

University Of California, Santa Barbara
FAQ

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What company does Christopher Tracy work for?

Christopher Tracy works for Self-employed.

What is Christopher Tracy's role at Self-employed?

Christopher Tracy is listed as ASIC Frontend Design and/or Verification at Self-employed.

Where is Christopher Tracy based?

Christopher Tracy is based in Santa Barbara, California, United States while working with Self-employed.

What companies has Christopher Tracy worked for?

Christopher Tracy has worked for Self-Employed, Raytheon Vision Systems, Sanbar Networks, Tality / Cadence Design Systems, and Cisco / Stratacom.

How can I contact Christopher Tracy?

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What schools did Christopher Tracy attend?

Christopher Tracy holds Master Of Engineering - Meng, Computer Engineering, Gpa 3.7 Out Of 4.0 from University Of California Santa Barbara.

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