Nuvoton Technology Corporation, Tainan. senior design verification engineer, 2021-2024.- Digital IC design front-end UVM (Universal Verification Methodology) verification environment establishment and verification program development applying in ARM core (M4) EC/SIO/BMC, computer peripheral applications, and cloud application IC.- High-level simulation environment construction and verification of digital IC design.Advanced Universal Verification Methodology (UVM), Object Oriented (OOP), and High-Level Verification Language to establish verification platforms, random verification sequences, and collect coverage data results. My experience with design verification is the computer output/input chips (Super I/O), notebook embedded controllers (EC), Trusted Platform Modules (TPM) leading, Server Remote Management Controllers in the global markets.- Major interface/ modules included UART, System configuration, PWM, GPIO, ITIM32, ROM, and BBRM. We created verification plans of the digital design blocks by following the design specifications and interacting with the designers to identify important verification scenarios. Create verification environments using SystemVerilog and UVM. Debug tests with designers to deliver functionally correct design modules and the regression simulation using Cadence vManager.