Representing the GIP Division Quality Management department in the companywide QM Digitalization effort, where I am responsible for identifying stakeholders, defining user needs, developing use cases and requirements, identifying and developing project scopes, tracking project development, along with collaborating with the other QM representatives to meet Infineon and Division QM stakeholder needs.Developed training and led initiatives to standardize and improve multiple QM business processes resulting in the creation and roll-out of standardized quality documentation, including a Risk Decision Template, which will soon be available for all of Infineon as a best practice.Acting as the QM lead on several companywide quality teams including the IPI Catalog and IPI guiding principles, Product Roadmap to Reliability planning, and the eQTP System.Responsible for the qualification of the multidie ARM based microprocessor family of iMOTION™ motor controller products along with other mutlidie devices consisting of gate drivers and switches.Defined product qualification strategies and created qualification plans in compliance with internal guidelines, external industrial JEDEC-47 standards, and customer requirements.Planned and executed product qualifications, which included defining stress hardware requirements for development by the hardware design team, evaluating qualification results with process and test engineers, and releasing the products with proper documentation.Supported the product development teams, which included assisting the project management and supply chain teams, defining project related risks, and creating regular reports on qualification readiness and status.

Managed the ISO 9001 based Quality Management System (QMS) and Office at one of the Navy’s Research, Development, Test, and Evaluation facilities.Supervised personnel to develop, plan, implement, and maintain the division’s QMS in accordance with Navy, ISO 9001, and ISO 17025 standards. Supervised the Audit, Facility Assessment, and Cause Analysis programs.Performed ~12 assessments / audits per year to analyze and evaluate major program/project activities to develop recommendations for improving the program's and process's effectiveness. Developed the Division’s Risk Management Program based on ISO 31000 and Failure Mode Effects Analysis processes.

Led the re-development and implementation of the Division’s Quality Management program due to a Navy re-alignment of the Carderock Division. Managed the Division’s Laboratory Quality and Risk Management Assessment Program that assessed the performance capability of Carderock’s testing facilities.Managed the Division’s Cause Analysis Program that determined root causes along with the corrective and preventative actions. Led audits and reviews of the Division’s Critical Programs to assess compliance with Navy requirements.

Analyzed and evaluated present and future program/project needs to recommend technical and economic tradeoffs for integrating subsystems, components, assemblies, and parts. Prepared detailed projections regarding costs, performance probabilities, and potential problems involved in modifying, eliminating, or introducing new technologies into Naval systems. Assigned engineering tasks to contractors and/or Navy Warfare Center personnel to meet future planning needs.

KGD and component level yield analysis on Low Power products in 200mm and 300mm facilities.Managed a program to identify, plan, and implement cost reductions, design modifications, test, process, yield, and quality improvements during the product and process development during the low power 70nm and 110nm DRAM and Known Good Die products ramp-up in a high volume DRAM manufacturing facility. Managed the Known Good Die test process transfer from Dresden, Germany to Richmond, VA, USA, which included developing and implementing a project plan for the transfer and installation of 8 Advantest testers and handlers, new equipment purchases and upgrades, process development, test method development and implementation, and quality assurance plans in the new electrical test and physical inspection process; ultimately became the KGD Product Line Owner. Responsible for the parametric test and process yield analysis, quality control verification, and customer fail root cause analysis along with the implementation of process and test improvements for the Low Power DRAM product line.

Module level functional and application test yield analysis.Drove finished product functional and application test coverage improvements, along with process yield improvements on commodity, and customized DRAM modules that reduced overall module DPPM rate to less than 200 DPPM. Led component and module product qualifications, to include package qualifications, logistic and test setup, failure root cause analysis using surface analysis, and scanning electron microscope techniques, and improving test coverage to cover for customer application failures.

Component level yield analysis in Dresden, Germany.Completed a 7-month delegation in Dresden, Germany for component test yield improvement on a Dresden-specific DRAM chip and transfer of a new DOE to the 200mm Dresden manufacturing facility.

Wafer level yield analysis on Infineon's first DDR product.