- IT follow-up: compute farm (LSF) + storage management to the design community and more generally at GPM level (300 designers)- Licenses management: Follow-up license usage, plan licenses purchases for GPM division + CS division (secure microcontroller) + RD division. Manage a budget more than 20M$.- Training to user and communications- Support on linux: VNC, LSF, Shell, EDA tools

- Responsible of analog tools support for MMS (Micro / Memory / Smartcard) group: ELDO simulation, FastSPICE, verification DRC / LVS, extracted parasitics.- In charge of software support for process simulation (TCAD) for Technology R&D team.- Support of tool which allows dispatch of jobs to a computer farm (LSF).- Responsible for data management: Administrator of versioning tool, clearcase, on Rousset site and as backup on Grenoble site. Work in multisite:… Show more - Responsible of analog tools support for MMS (Micro / Memory / Smartcard) group: ELDO simulation, FastSPICE, verification DRC / LVS, extracted parasitics.- In charge of software support for process simulation (TCAD) for Technology R&D team.- Support of tool which allows dispatch of jobs to a computer farm (LSF).- Responsible for data management: Administrator of versioning tool, clearcase, on Rousset site and as backup on Grenoble site. Work in multisite: Rousset/Grenoble/Tunis/Catane.- Licenses management for design application (floating flexlm license).- Support use environment on 2 sites Rousset and Zaventem (Belgium) Show less

Responsible for developing Designs Kits for RF flow, circuit design in 0.25um BiCMOS technology and HCMOS under Mentor and Cadence.- Development of Mentor kit: put in place models, symbols, DRC, LVS...- Customization of Cadence kit: development of skill routine, procedure of migration.- Put in place validation method to ensure the quality of design kit.- Manage customer requests in order to plan implementation in Design kits in collaboration with CR&D.- Support for… Show more Responsible for developing Designs Kits for RF flow, circuit design in 0.25um BiCMOS technology and HCMOS under Mentor and Cadence.- Development of Mentor kit: put in place models, symbols, DRC, LVS...- Customization of Cadence kit: development of skill routine, procedure of migration.- Put in place validation method to ensure the quality of design kit.- Manage customer requests in order to plan implementation in Design kits in collaboration with CR&D.- Support for internal designers (~100) Show less

CAD tool development which allows parasitic extraction of inductances on RF chips:- Implementation of the methology by using FastHenry- Development of the extraction flow by using skill programs. From a layout and technology datas, a file is built to be able to be used by FastHenry- Tool deployed and used by all RF designers (~50)

Characterization and Modelization of transistors in technology SOI 1.2um:- Implementation of the software "Utmost3" from Silvaco.- Modelization of MOS transistors with BSIM3V3 model- Models delivery for chips dedicated to an European space project.