As the most senior metallization expert at Intel, envisioned and led initiatives in novel materials and integration flows in nodes from pathfinding to production to improve power, performance, and price.• Co-chair of the Integrated Module/Patterning Advanced Component Technology meeting, for Director level review of Foundry TD roadmaps for Intel 4 through 14A, and beyond. • Core member of the Intel LTD Industry Forum for Technology which drives alignment between equipment supplier development roadmaps with Intel’s silicon technology roadmap.

Led 5 different Chemical Vapor Deposition groups doing advanced node development for contact metallization, gate fill, work function metal, local interconnect fill, via fill, as well as novel memory layers. • Managed combined D1 (TD and Manufacturing) advanced metals groups totaling 40+ engineers.• Chair of Advanced Module Review meeting for Director review of Thin Films/CMP roadmaps.

Chair of P1276 Metal Gate Focus Team from pathfinding through to Intel3 production. Initiated a Thin Films/Planar department training effort in support of LTD wide cultural reset effort. • Led taskforces to select and develop new metal gate materials/integration schemes for Intel4/3.• Created and taught training classes on topics such as: Intel’s process flows, CVD deposition, plasma processing, SRAM devices, career development, and semiconductor industry history.

Led group that delivered the first HVM implementation of cobalt local interconnect at the 10nm node. • Led selection and development of first in industry high throughput CVD metals equipment. • Led internal development of proprietary PE CVD/ALD barrier/liner to enable Co integration.

Led group that owned all LTD front-end metallization module development -- Metal gate, silicide, and local tungsten interconnect for Intel’s 45nm, 32nm, 22nm, and 14nm nodes. • Directly managed a pilot line fleet of over $100M in metals deposition equipment which was successfully “Copied Exactly” across Intel’s factory network and ramped to HVM in each node.• Led taskforces to re-engineer the transistor source/drain contact and gate fill integration schemes required for the 3D “tri-gate” transistors used in Intel’s 22nm, 14nm, and 10nm nodes.• Invented scalable CVD metallization solutions to replace PVD metals in FinFET integration scheme: CVD W gate fill (used at 22nm) and conformal Ti wrap around contact (used at 10 nm). • Grew the group from 4 to 18 PhD engineers. Owned recruitment and candidate selection.

P1266 Metal Gate module/tool owner. Ran taskforces to establish process and tooling HVM readiness.• Developed a novel work function metal (WFM) and Atomic Layer Deposition barrier, as well as associated tooling for Intel’s 45nm node -- the world’s first HVM high-k metal gate technology.• Worked with suppliers to bring the industry’s first integrated PVD/ALD tools to HVM.

P860/1260/1264 Copper Barrier/Seed module/tool owner.• Module owner for Intel’s first Cu Barrier/Seed deposition process at the 0.13um node. • Selected 300mm Cu B/S process equipment and owned module development activity for the world’s first 300nm wafer size technology to ramp to high-volume manufacturing (HVM) “P1260”.• Led team to develop and qualify a second source supplier for Cu B/S equipment at 65nm.