Dane Aiken Email & Phone Number

Austin, Texas Area

Perform system administration tasks for PC networks. Configure new PCs and add them to the network. Troubleshoot PC and network problems.

Austin, Texas Area

Designed video codecs based on JPEG2000 image compression standard.ADV202 - JPEG2000 Video Codec (ARM-based SoC)• Designed rate control, AHB interface, and codeblock sequencer modules - all components of the entropy coder.• The rate control logic incorporates the first-known hardware implementation of a convex hull algorithm.• Designed a floating-point adder for the convex hull hardware and devised a novel method of calculating distortion-length slopes without the complexity of a hardware divider.ADV212 - Second-Generation JPEG2000 Video Codec• Restructured rate control hardware for significant area savings by replacing a register bank with a two-port register file and modified control logic.• Implemented new features in the entropy coder and enhanced the entropy coder test environment.• Investigated a problem customers had experienced since the introduction of the ADV202. Researched the JPEG2000 standard, comparing it to the externally-provided algorithmic model for the arithmetic coder. Discovered an error in the bytelength calculation algorithm. Developed a new method of determining bytelengths and incorporated the corrected algorithm into the C++ model of the arithmetic coder. Implemented the corresponding hardware fix in verilog.• Led production test and evaluation strategy. Supported product engineering team in silicon bring-up, characterization, and qualification. Led weekly production test strategy meetings between design and product engineering. Managed production test suite. Devised an improved method of test vector translation.Improved an existing SPI design by adding additional transfer modes and doubling the maximum serial clock frequency.Designed a block to arbitrate between two SPI modules in an FPGA implementation of a camera processor.

Austin, Texas Area

Architected variable-length decoder for a wireless MPEG-4 processor.Designed address generation unit for APEX (a DSP core for telephony applications). Custom-designed some of the logic to meet performance specs.Synthesized the entire APEX core and integrated it into a Caller ID with Call Waiting design. Two previous versions of the core were a combination of custom circuit design and synthesis. Subsequently became the go-to person in the division for synthesis help.Developed the first timing-driven layout flow in the division using the APEX core as a test vehicle. This methodology employed the forward-annotation of path constraints from synthesis to place and route and was adopted for use on later division designs.Designed voice codec and data codec decimation filters for an analog front end.Designed datapath for DSP engine of second-generation ADPCM codec (a mixed-signal telephony IC).Received award for significant contributions as member of IP Deliverables Development working group (part of Motorola Semiconductor Reuse Standards).

Austin, Texas Area

Led new product development of ADPCM transcoder and ADPCM codec ICs. Identified packaging, set up production documents, coordinated with test engineering and design to develop the test plan, test hardware and software. Performed characterization and qualification.