Daniel Cummings Email & Phone Number

Austin, TX, US

Santa Clara, California, US

• Developing innovative solutions for a variety of problem domains at Intel.Engineering activities include:
• Memory compiler development on cutting-edge process technology nodes.
• Designing AI-centric design automation and quality assurance tools.
• Supporting competitive benchmarking efforts.AI/ML Research activities include:
• Multi-objective optimization techniques applied to unique design automation problems.
• Research and development of novel optimization solutions for generative AI / LLM / Transformer architectures.

• Built out AI/ML solutions for a variety of government applications.
• Rapid prototyping and benchmarking of novel deep learning computer vision algorithms (e.g., detection, classification, segmentation) and MLOps through Microsoft Azure.
• Drove R&D effort for customizing Large Language Models (LLMs) to enable user-friendly UI/UX capabilities such as video-to-text summarization, Q&A, and document summarization.
• Deep learning model compression and neural architecture search (NAS) for hardware-aware performance optimization to enable edge deployable computer vision applications. Fundamental research on pruning for sparse neural.
• Led scoping and enablement of multimodal/multi-view sensor fusion solutions (NeurIPS '23 publication) that beat state-of-the-art performance on re-identification benchmarks.
• Supported business development efforts by developing ML system prototypes based on customer requirements and defining the R&D roadmap for emerging AI technology applications.

Hillsboro, OR, US

• Performed research at the intersection of deep neural network algorithms and hardware (6 patents filed).
• Developed hardware-aware neural architecture search (NAS) methods that leveraged bi-level optimization approaches paired with evolutionary algorithms. Resulted in a 4-10x speedup in the search process.
• Demonstrated a method for joint hardware-accelerator and deep neural network architecture optimization across a variety of performance objectives.
• Researched algorithmic approaches for exploring large-scale combinatorial search spaces as related to the modern chip design flow.
• Adapted temporal graph neural network algorithms for business intelligence applications.

Santa Clara, California, US

• Built software framework to aggregate, categorize, and plot artificial intelligence research trends using academic graphs, conference data, and graph neural networks.
• Developed a graph neural network citation prediction model to determine which recently published papers are likely to become the most popular. Paper presented at ICASSP 2020.

Santa Clara, California, US

• Memory compiler architecture technical design lead on four generations of cutting-edge process technology nodes.
• Developed lightweight programs and dashboards in Python to support competitive performance projections, quality assurance, and anomaly detection.
• Served as a customer interface, project manager, and technical contributor for an interdisciplinary team spanning design, mask layout, and software.

Santa Clara, California, US

• Novel memory circuit architecture research to enable best-in-class timing performance and lower power consumption. (7 patents granted)
• Memory compiler development on leading-edge technology nodes to enable company-wide adoption of industry-standard foundry compilers.
• SRAM circuit design, floor planning, timing convergence, and low power optimization for multiple novel technology nodes to meet customer performance specifications.

Gainesville, Florida, US

• UF Software & Analysis of Advanced Materials Processing Center (SWAMP):
• Performed numerical physics modeling of solar radiation effects on modern space-borne electronics to predict soft-error rates in modern CMOS topologies. Funded by AFRL and NASA. (5 Publications)
• Software tool development in C++/Tcl for the Florida Object Oriented Device Simulator (FLOODS) to enable adaptive grid techniques and extend strained-Silicon modeling capabilities.
• Developed numerous physical models for radiation effects simulations including a novel process-induced stress mobility variation model for charge collection.
• Consulting work for two companies: researched device-level SRAM reliability under extreme environmental conditions using various SOI manufacturing approaches.

Washington Navy Yard, DC, US

• Granted Final Secret Clearance, NATO Secret Clearance
• Collected field experiment data for countermeasure systems and applied statistical methods for littoral capability success prediction.
• Conducted physics-modeling, analysis, and simulated environment studies for various countermeasure systems.
• Co-authored 428-page Department of Defense sensor technology report that recommended how remote electro-optic, thermal, microwave, and seismic technologies could be employed to support Homeland Security capabilities.

Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering

Master Of Science (M.S.), Electrical And Computer Engineering

Bachelor Of Science (B.S.) - Cum Laude, Electrical And Computer Engineering