Dan Sides Email & Phone Number

Hillsboro, Or

-QuickPath Interconnect (QPI) Link Layer Design -Verilog design, synthesis and simulation.

• Designed link layer for next generation, QuickPath Interconnect (QPI) in Verilog. QPI link layer provides reliable, point-to-point cache coherent transfer of data between processors. • Design included full-duplex, high speed header & data processing, retry control, generation &servicing, control packet parsing & generation, credit usage & tracking, header & data pipelining, & CRC checking & generation. • Developed link layer architecture, implemented Verilog RTL design, & performed unit level simulation. • Ran system level simulation/verification & debug. • Revised an existing LRU design for improved system performance. Wrote Verilog RTL. Performed high speed synthesis, place & route, & static timing targeting Altera & Xilinx FPGAs. • Also implemented Signaltap embedded logic analyzer for existing FPGA design.

Hillsboro, Or

Design & Verification of Platform Management Control Chipsets • Designed & verified fault logging buffer intellectual property (IP). Design buffered ingress data frames for storage to non-volatile memory when board fault is detected. Featured pre-emptive storage architecture, WISHBONE slave interface, interrupt & timestamp. Configurable user opcodes, frame width & memory implementation. Wrote specs, designed & implemented Verilog & unit level tested. • Designed & verified full-duplex, self-synchronous, chip-to-chip serial interface. IP was configurable per frame size, memory size & type & data length widths. Featured CRC & ACK checking & error counting. Designed, implemented & verified Verilog, wrote design & verification specs, & validated in hardware. • Both IPs were delivered ahead of schedule with no bugs found during system level verification. • Intellectual property lead engineer. Responsibilities included approving technical specifications, usage models & software GUIs. Provided project reports, attended project summits & status meetings.

• Managed low density & mixed signal applications group, with locations in Hillsboro, Bangalore, & Shanghai, reporting to Corporate Vice President. • Set annual goals & gave reviews for 14 employees (13 engineers & one manager). • Directed the delivery of marketing collateral for three new Lattice products. This includes scheduling & approving reference designs, tech notes, usage models, evaluation boards, & eval board demos. • Increased number of reference designs from 8 to over 50 within two years. • Directed customer evaluation board design, debug & production for 10 new evaluation boards. • Started Bangalore low density applications team.

● Supported Tier 1 customer FPGA projects: Verilog & VHDL RTL design work, simulation support,reference designs, & lab debug.● Wrote usage models, tech notes, blogs & magazine articles.● Worked tech support & ran tech support metrics.● Created reference designs & FAQs.● Wrote & presented customer & FAE training material & webcasts.● Visited customer sites & attended trade conferences.

Hillsboro, Or

Front end validation for enterprise chipsets: • Performed post layout gate level simulation (GLS) effort for a dual core, Xeon north bridge chip with PCI-Express & FBD support. • Built GLS environments, regressed test suites, wrote Perl automation scripts & debugged tests. • Performed first silicon functional testing on an Agilent tester.Front end ASIC design/verification for telecom edge termination equipment: • Designed & documented an HDLC framer & generator for an OC3 stream from a SONET Framer/Mapper. • Led the verification environment effort for an HDLC/ATM datalink controller. Wrote test plan, built Specman environment & wrote tests. • Architected queueing layer flow control for cell/packet store & forward buffering.

Raleigh, Nc

Front end design and product definition for network processors and metro area network devices.• Led a 4 person team in a feasibility assessment of producing a 10 Gbps WAN mode Ethernet to OC192 SONET bridge ASIC.• Designed a high performance, pipelined policer and statistics manager for a 40 Gbps IP network processor.• Designed a frame buffer pointer queueing system for a 10 Gbps IP network processor.• Team was acquired by Intel.

Raleigh, Nc

• Provided on-site design, test and implementation consulting for tier 1 customer engagements. • Assisted with sales calls, statements of work, & consulting estimates. • Designed (Verilog) the receive side of an ATM based set-top-box ASIC, connected to a fiber-to-the-curb broadband network. Also wrote test plan. • Implemented a cable modem board verification environment, resulting in full customer adoption. • Performed static timing for customers. • Converted LSSD PowerPC microprocessor VHDL design to a rising edge, flip flop implementation with gated clocks & muxed feedback.

Ms, Electrical Engineering

Bachelor'S Degree, Mathematics