Working as Physical Design Engineer at Incise Infotech Pvt Ldt.Familiar with ASIC Design flow, starting from RTL to GDSII. Having technical exposure on Floor Planning, Place and Route, Clock Tree Synthesis, Timing Analysis, DRC/LVS. Worked on technology nodes like 7nm 14nm 22nm 28nm.Worked on PV fixes using Fusion Compiler and sign-off using Cadence Virtuoso Calibre. Hands-on experience on EDA tools SYNOPSYS ICC2 , Fusion Compiler, Cadence Innovus, Calibre and Cadence Virtuoso.• Masters from University of Bristol, UK (2017-2018).• BE from Visvesvaraya Technological University, India (2013-2017).