David Brantley Email and Phone Number

Doing P&R work remotely

Supporting Physical Design Kits (PDKs) for internal and external customers for PCB and MCM designs

Performed P&R duties on digital logic for one of the mixed signal design groups. Work used Cadence P&R tools, both encounter and innovus. Ran extraction using Star. Checked power results using Voltus. Brought routing results into Cadence Opus and ran DRC/LVS/Antenna verification decks. Once all checks passed, the routed blocks were passed on to layout for incorporation into the rest of the chip.

Doing place and route on digital blocks to be used on analog/mixed-signal/RF designs. Using Cadence Encounter suite of tools. Using both physical only and timing-driven flows to take gate level Verilog netlists out thru tapeout ready designs. Developing Cadence Skill routines when needed to help both full custom and P&R portions of the design. Maintaining/enhancing foundry supplied PDK's and physical verification decks in Cadence Assura. When not busy with IC design and support duties, busy… Show more Doing place and route on digital blocks to be used on analog/mixed-signal/RF designs. Using Cadence Encounter suite of tools. Using both physical only and timing-driven flows to take gate level Verilog netlists out thru tapeout ready designs. Developing Cadence Skill routines when needed to help both full custom and P&R portions of the design. Maintaining/enhancing foundry supplied PDK's and physical verification decks in Cadence Assura. When not busy with IC design and support duties, busy supporting 140+ hardware designers installing engineering tools from 15-20 vendors on both PC and Linux platforms. Also maintain licenses and quotes for both maintenance of existing tools as well as new tool purchases. Doing the day-to-day support of the hardware engineers whenever they encounter problems using the tools. Show less

Developing custom design flows in Cadence Skill to automate the placement and routing of designs in different super-conductivity processes using the RQL design methodology. Create libraries of primitive cells using the Pcell and CDF parameter design paradigm. Automate the design process wherever possible in Skill to help bring super-conductivity more into the mainstream of design options.

Develop design flows for digital blocks to be integrated into mixed-signal/RF chips. Worked mostly in a Cadence Encounter environment at 180 and 130 nodes to match the analog. Most recent work was developing both a Cadence Velocity and Synopsys IC Compiler flow for TSMC 40nm. Maintain Physical Design Kits (PDK’s) from different foundries at various technology nodes to support RF/mixed-signal design work. Maintained DRC/LVS decks in all targeted nodes using a mix of Cadence Assura/Diva and… Show more Develop design flows for digital blocks to be integrated into mixed-signal/RF chips. Worked mostly in a Cadence Encounter environment at 180 and 130 nodes to match the analog. Most recent work was developing both a Cadence Velocity and Synopsys IC Compiler flow for TSMC 40nm. Maintain Physical Design Kits (PDK’s) from different foundries at various technology nodes to support RF/mixed-signal design work. Maintained DRC/LVS decks in all targeted nodes using a mix of Cadence Assura/Diva and Mentor Calibre. Develop custom Skill programs to aide in the physical implementation of designs. Show less

Lead physical design team which implements internally developed DSP cores in both internal and external technologies for characterization for customers. Working primarily with .13um technologies, but have also done .35um, .25um, .18um and 90nm for various foundries. Develop test chips to verify the DSP cores in silicon. Tools used include: Jupiter, Apollo, Astro, StarRC, MarsRail, PrimeTime and Physical Compiler from Synopsys; Opus from Cadence; Calibre from Mentor; as well as in-house tools.

Accept customer supplied, gate level netlists and produce a chip ready for fabrication. Create the floorplan, execute place and route, run all backend DRC and LVS checks, extract back-annotation data to return to the customer, and close timing issues. Tools used include: PrimeTime,Design Compiler, Chip Architect, Physical Compiler, Arcadia from Synopsys; CTGen, Silicon Ensemble, Design Planner, Opus from Cadence; Calibre from Mentor; Fire and Ice from Simplex; as well as in-house tools.

Came to Dallas Semiconductor to create a centralized CAD support group.Responsible for evaluating, purchasing, implementing, and supporting design automation tools for all phases of design. Supported both full custom and Structured Custom design methodologies. Put in place automatic place and route tools for cell and block level, synthesis tools, and high-level ESDA tools. Led the conversion from Cadence Edge to Cadence Opus. Responsible for a team of ten people to be the core CAD support… Show more Came to Dallas Semiconductor to create a centralized CAD support group.Responsible for evaluating, purchasing, implementing, and supporting design automation tools for all phases of design. Supported both full custom and Structured Custom design methodologies. Put in place automatic place and route tools for cell and block level, synthesis tools, and high-level ESDA tools. Led the conversion from Cadence Edge to Cadence Opus. Responsible for a team of ten people to be the core CAD support group for the company. Managed a yearly capital budget of $5M and a yearly non-capital budget of $3M. Show less

Worked on specialized projects for various Cadence customers. Projects included an automatic place and route system for datapath circuits, automated RAM/ROM generators based upon designer inputs, emulation of installed layout products to ease the training and transition period to Cadence products, developed specifications and a prototype version of a Cadence/SCICARDS interface, and worked with Cadence products to migrate layouts of existing circuits to newer processes. Projects were done in… Show more Worked on specialized projects for various Cadence customers. Projects included an automatic place and route system for datapath circuits, automated RAM/ROM generators based upon designer inputs, emulation of installed layout products to ease the training and transition period to Cadence products, developed specifications and a prototype version of a Cadence/SCICARDS interface, and worked with Cadence products to migrate layouts of existing circuits to newer processes. Projects were done in SKILL, an internal graphic programming language with C syntax and Lisp data structures. Work was done on UNIX platforms under the X Windows environment. Show less