Patent classification, patent product mapping, reverse engineering, and infringement analysis.

• Prime/author of technical feasibility studies for Qualcomm-based handsets. Evaluate hardware and software at systems level to ensure marketing requirements (battery life, performance, cost, etc.) are achieved. Identify key risk areas early in design cycle for downstream development groups.• Lead team of system architects in analyzing architectural impact of carrier requirements on 2G/3G/4G cellular radio and platform dependencies.

IDT is a diversified semiconductor manufacturer of consumer, networking, and computing components. Chief Architect Networking DivisionDirector of Architecture for Search Engine division (TCAM and algorithmic), reporting directly to division general manager.As primary interface to OEMs, identified breaking points in customer architectures to drive next-generation product direction, features, and concepts.Responsible for driving primary research, proof-of-concept, requirements, and functional specifications of future products.Instrumental in creating an industry shift to standards-based serial interfaces for TCAMs by initiating working groups as well as authoring both the Interlaken-LA (look-aside) and OIF SLA (Optical Interworking Forum Serial Look-Aside) standards. Managed Intellectual Property (patent) portfolio development within the division including personally authoring 15 patent filings.First (and only) nominee for IDT Fellow Program.Technical analysis of competitive technologies (home-grown OEM solutions, acquisitions, and merchant vendors).Co-inventor of patent-pending B-tree algorithm base technology for IDT Route Accelerator, a low-power fully self-managed search engine family for Layer 2-4 exact and prefix match applications.Co-inventor of algorithmic Access Control Lists (full wildcard search) solution based on novel set splitting techniques.Co-inventor of novel range match circuit requiring only 21 transistors per bit (less than half the best published solution).

A well-funded 3rd generation Network Processor startup, SNI produced the world's first 20Gbps Network Processor, Traffic Manager, and co-processors.; Company leader (CTO equivalent) in terms of system definition, product direction, and feature content of world's-first 20G Network Processor (NPU), Traffic Manager (TM) and co-processors. Industry recognized as the only credible full-featured solution to complex routers and switches. Directed architecture teams that delivered first-time working silicon on 4 complex leading edge 130nm ASICs.Custom multi-threaded NPU with 32 CPUs, 256 threads, and high speed SPI-4 protocol for line, fabric and co-processor interfaces. A major OEM is actively developing an in-house 40G NPU based on the intellectual property from this NPU.Full-duplex traffic manager utilizing industry-first patented heap-based scheduler, permitting rate shaping and weighted fair queuing with infinite precision.Defined industry-first TCAM with patented integrated range matching and ECC protection.As primary interface to OEM clients, provided analysis of their forwarding requirements and front-line sales support to establish multiple design wins. Key contributor in Network Processor Forum working groups defining look-aside LA-1/2, and fabric interface (NPSI) protocols.

Networking OEM specializing in carrier grade TDM, ATM, and IP routing.Technical Specialist Level 7Member of cross- functional architecture team responsible for the design of carrier scale Inter-networking products. Architected products through off-the-shelf merchant silicon, acquisitions, or in-house ASIC development.Performed technical evaluations of third party components and systems for potential use in current and future product developments, including first and second generation Network Processors from LSI (Atomizer), MMC (PSP and EPIF), Intel (IXP1200), IBM (Rainier), Agere, Sitera, and C-Port.Performed due diligence on potential acquisition candidates.Designed patented multi-field classification ASIC.Designed ASIC search engine for IP prefix matching, MAC, RSVP, and string matches, patented identical version of industry recognized "Eatherton" algorithm.Architected, designed, and implemented wire-rate MPOA edge router, 24 FE ports and OC3/OC12 uplinks. Designed embedded software for ATM NICs for Sun, SGI, and Windows.

As one of the earliest data communications OEMs, Gandalf pioneered modems and data PBXs.; Real-time system design for statistical data multiplexers, data PBXs, and LAN/WAN bridges/routers.Extensive data compression expertise included patented Limpel Ziv Arithmetic algorithm for family of remote bridge/routers. Authored IETF RFC1717, 1990, and 1993.Hardware IP/MAC search engine for multi-protocol WAN router.

Leading OEM of RF paging terminals.Hardware/Software DesignerHardware module design and software for RF paging terminal, including device drivers, OS porting, and application software.

A startup focused on the development of an integrated word processing terminal.ProgrammerApplication software development (Pascal/Assembler)