David Donofrio Email & Phone Number

The Computer Architecture Group is a team composed of scientists, engineers, postdoctoral fellows and students focused on the research and development of technologies, algorithms, and architectures that enhance the performance, scalability, and energy efficiency of the Department of Energy's multicore-, manycore-, and accelerator-based supercomputers. In addition, our group is influencing future architectures for all aspects of scientific computing ranging from field deployable sensors to the largest HPC systems. Research supported by multiple (seven) external agencies and spans multiple, diverse science domains including high-speed simulation, rapid hardware generation, specialized accelerator research, real-time signal processing applications for neuroscience research, device modeling, bioinformatics, electric grid modeling and transportation research.

Cupertino, Ca

Responsible for the system performance of all Mac computers – (iMac, MacBook, MacAir, MacPro, etc.) from concept phase to just before production. Requires knowledge of full system stack from circuit design, low level driver and kernel details all the way up through applications to the user interface. Continuous interaction with cross functional groups to root cause hardware, OS, driver and application performance issues. In addition, heavy interaction with hardware vendors who supply components for Apple products to debug functional and performance issues. Responsible for creating performance projections of future products, evaluating the performance of prototype systems and ensuring continued good performance on current shipping systems.

The current approach to HPC design is approaching its limits as costs to power HPC systems is exceeding procurement costs. My primary responsibility is to analyze the performance and customize the architecture of an embedded processor that will be the building block of a future HPC system designed to model the climate at 1 km scale resolution. Performance analysis is being done using the Berkeley RAMP FPGA platform.

Started in the rotation engineers program working in Flash memory, Graphics Architecture and Analog Circuit DesignPrimarily responsible for building a performance simulator in C++ to model Inel's integrated graphics core. In addition, was responsible for the HW architecture of an extended math unit capable of calculating the trig and transcendental functions in IEEE single precision floating point.