David Grundmann Email & Phone Number

Marlborough, Ma, Us

* Lead developer for EDA tools integration from leading vendors, incorporating new features, tools, and methodologies for flow simplification and power reduction identification* Leadership in development of tools from concept to finish for design execution, constructing new tools for SoC power rollups, fsdb quality, EDA tool version quality to library, EDA API for custom mapping solution, ease of use tool for collateral generation for hundreds of designers * Team collaboration on developing full flow for power execution, working with collateral inputs from other teams and infrastructure development * Identifying issues in quality of signal activity resulting in faster identification of bad stimuli before power runs* EDA communication and synchronization to resolve problems like bugs or analysis concerns and negotiating new features for quality assessments* Drove 40%-80% runtime reduction in key problem areas of tool execution utilizing python and report optimization* Solving of new construction methodologies to close gaps in power analysis* Resolved gaps in power estimation with custom quality checkers and fixers* Made tool to universally generate power density maps, bridging gaps between power estimation, bump IR, and package thermal guard bands.* Direct support with users of power tools, debugging and resolving questions and problems encountered. Taking feedback and modifying documentation accordingly.* Invested into Generative AI for coding using GPT and GitHub-copilot, accelerating development of simple tools for data analysis and ML components.* Oversaw team building activities to explore opportunities, brainstorming, and exploring new and meaningful methodologies. Resulting to better power saving techniques, goals and KPIs, and latest tool understanding to unify power team knowledge.

* Power domain lead for small server project, managing power targets and execution tasks for 20+ designs* Power tool expert for 6 Server projects, providing primary support, training, and enhancements to over 200 engineers. * Outlined the structure for collaborative work with junior member on load share of support tickets, review of tickets every month to identify trending issues for solutions, and coding share. * Mentored at least 6 junior members on tool execution, debugging techniques, and programming practices in TCL and Perl. * Trained 12 expert users and section power leads on power tool executions, debugging techniques, and data gathering for reduction opportunities. * Invention of initial power rollups and data analysis tools leading projects to identify and reduce overall power and resolve domain power issues* Cross-domain collaboration enabling new construction methodologies in domain

* Innovated XLL tool for Excel based power density map generation enabling capabilities to rapidly do what-if scenarios for turbo, binsplit, bump IR risks, and package thermals. Enabled defeaturing studies for die-chop definitions* Developed power tool, Intel specific, automation flow for execution of over 700 designs* Defined and created basic scripts for data gathering for power density, project trends, and binsplit handoff

* Design intern working on L2 RAM* SER studies and analysis, building custom tool to assist in studies and variations* Developed custom RAM characterization tool using spice.

Intern design engineer for DEG in Hudson, MA. Worked on IA64 caches in implementation, simulation and feasability