David Halter Email & Phone Number

Austin, Texas Area

My responsibilities include:PLL characterizationI/O driver characterizationSerDes characterizationCustomer support and return issuesTest card design and development, This includes, a review test card printed circuit board (PCB) design and layout for signal integrity issuesCreated infrastructure to automate bench level testing using a Python based environment to communicate with equipment over GPIB, Ethernet, and serial interfaces.Conducted ATE to bench… Show more My responsibilities include:PLL characterizationI/O driver characterizationSerDes characterizationCustomer support and return issuesTest card design and development, This includes, a review test card printed circuit board (PCB) design and layout for signal integrity issuesCreated infrastructure to automate bench level testing using a Python based environment to communicate with equipment over GPIB, Ethernet, and serial interfaces.Conducted ATE to bench correlationHelped guide and support Freescale/NXP’s validation lab in IndiaMeasure test card PCB impedance profile using time domain reflectometry (TDR)• Lab Equipment includes:• Tektronix DSA 72504D Digital Serial Analyzer, Oscilloscope• BERTScope BSA 125B-PCIE, BERT• Numerous power supplies, clock sources, parametric analyzers and multi-metersPatent US 7777509"Method and apparatus for electrical testing" Show less

Austin, Texas Area

Responsible for testing and characterizing analog IP for SoC and designing testcards for use in verification. This includes analysis on PLLs, I/O drivers, power delivery and system level debug of testcards. • Characterize a PLLs, transfer functions, jitter analysis, lock times, hold-in/pull-in and stability.• SerDes transmit eye testing.• I/O driver rise/fall times, bus timings (setup and hold).• Power supply noise and PSR analysis.• Helped design test card printed… Show more Responsible for testing and characterizing analog IP for SoC and designing testcards for use in verification. This includes analysis on PLLs, I/O drivers, power delivery and system level debug of testcards. • Characterize a PLLs, transfer functions, jitter analysis, lock times, hold-in/pull-in and stability.• SerDes transmit eye testing.• I/O driver rise/fall times, bus timings (setup and hold).• Power supply noise and PSR analysis.• Helped design test card printed circuit boards (PCB) design and layout for signal integrity issues.• Supported production yield impacts.• Conducted ATE to bench correlation.• Helped guide and support NXP’s validation lab in India.• Worked with an external vendor to support characterization for which NXP did not have the appropriate equipment. This included working with external vendor developing tools needed to do our work. Did many years of work with Tektronix on O-scope and probe development.• Measure test card PCB impedance profile using time domain reflectometry (TDR).• Lab Equipment includes:• Tektronix DSA 72504D Digital Serial Analyzer, Oscilloscope• BERTScope BSA 125B-PCIE, BERT• NoiseCom Programmable Noise Generator JV9075• Numerous power supplies, clock sources, multi-meters• Customer support and return issues.• Numerous sampling Oscilloscopes. Show less

Austin, Texas Area

1989 to 1998 - IBM: PCB Design, System, EMC, Thermal, ESD and Acoustic Engineering. This included schematic entry and PCB physical layout. Worked on system issues and customer issues. The projects worked on were the RS/6000. For the RS/6000, I was the lead card design Engineer for the mother board (I/O planar). I was also the lead engineer for the “Deep Blue” (later “Deep Thought”) I/O planar. This was a massive 512 node computer with four processors per node. My… Show more 1989 to 1998 - IBM: PCB Design, System, EMC, Thermal, ESD and Acoustic Engineering. This included schematic entry and PCB physical layout. Worked on system issues and customer issues. The projects worked on were the RS/6000. For the RS/6000, I was the lead card design Engineer for the mother board (I/O planar). I was also the lead engineer for the “Deep Blue” (later “Deep Thought”) I/O planar. This was a massive 512 node computer with four processors per node. My I/O planar hosted four CPU cards.Patent issued at IBM: US 6421619"Data processing system and method included within an oscilloscope for independently testing an input signal." Show less

Bs In Engineering, Electrical And Electronics Engineering

Activities and Societies: Tau Alpha Phi - This is Nnational Honor Society for Electronic Engineering Technology that recognizes the top 4%.

High School Diploma

Activities and Societies: Chess Chess Club