David Greeson Email & Phone Number

Rtp, Nc

Detail-oriented Software Design engineer with 21 years of success completing 16 major company projects. Known for thorough testing and craftsmanship of products to benefit the company. Served primarily as a Software Design engineer, and have also worked as an ASIC Verification engineer and a Diagnostic engineer. Major projects involved developing BIOS and bootloader for Intel-based and ARM-based products; designing firmware for microcontrollers; and writing device drivers for serial, E1T1… Show more Detail-oriented Software Design engineer with 21 years of success completing 16 major company projects. Known for thorough testing and craftsmanship of products to benefit the company. Served primarily as a Software Design engineer, and have also worked as an ASIC Verification engineer and a Diagnostic engineer. Major projects involved developing BIOS and bootloader for Intel-based and ARM-based products; designing firmware for microcontrollers; and writing device drivers for serial, E1T1, Ethernet, I2C, MDIO and JTAG interfaces.BIOS Security – Incorporated BIOS vendor code changes to support the UEFI standard BIOS write-protection and secure BIOS updates for Intel-based modules. As hackers become more sophisticated with their attacks, there is an urgent need to implement UEFI standards to protect the BIOS against attacks and provide a secure update method.• Worked closely with the BIOS vendor to resolve design issues in vendor’s code and overcome platform hardware design limitations.• Corrected issues caused by a previous security feature implementation.Intel-Based Platforms – Worked with a team to port the proprietary BIOS bootloader application to a new Intel-based platform. The existing bootloader accessed the hardware directly, which consumed an excessive amount of time to port the bootloader to new platforms.• Promoted use of BIOS drivers to make the bootloader more portable and reduce initial bring-up time for new platforms. The BIOS provided stable, well-tested driver code.• Met bring-up deadline by porting existing Ethernet driver and TFTP code to newer Intel GE MAC. Later made functionality more robust by replacing the Ethernet driver and TFTP code with the BIOS IP stack and Ethernet device driver.• Recommended that the hardware team use the FPGA to interpret PHY LED signals to drive Cisco-standard port LEDs. This change allows the customer to determine the link state without initiating a TFTP download, and is now used in newer platforms. Show less

Rtp, Nc

FPGA Verification – Met tight deadline to implement a solution for a billion-dollar family of products after an ASIC fabrication plant was destroyed in a Japan tsunami. Worked with a team to develop an FPGA version of the ASIC, enabling continuous production of six product lines, and preventing a potential 12-month loss of sales.• Successfully reconstructed four test benches, which included revamping them to use a new tools version, and modifying test harnesses.• Restarted… Show more FPGA Verification – Met tight deadline to implement a solution for a billion-dollar family of products after an ASIC fabrication plant was destroyed in a Japan tsunami. Worked with a team to develop an FPGA version of the ASIC, enabling continuous production of six product lines, and preventing a potential 12-month loss of sales.• Successfully reconstructed four test benches, which included revamping them to use a new tools version, and modifying test harnesses.• Restarted continuous regression runs in order to increase FPGA verification test coverage. Triaged failures uncovered by the regression runs.• Learned to read and understand Verilog code.ASIC Verification – Worked with a team to verify a new core ASIC for next-generation routing platforms.• To increase test coverage and make better use of available CPU resources, heavily modified Perl script to run continual regressions throughout the day and to vary the regression load based on the time of day. These continual regressions found 90+ bugs in the verification test benches and 10+ errors in ASIC code.• Took ownership of the GPIO verification test bench. The test bench had multiple regression failures and had been pulled out of regression runs because it was detecting too many false errors. Cleaned up the failures in the test bench, which enabled it to detect a spurious interrupt in the GPIO ASIC code.Next-Gen Platforms – The next-generation platforms were built around a new ASIC, which combined the functionality of several FPGAs. Worked with a team to develop and port existing device drivers for next-generation platforms that used the ASIC. During my driver development and testing, discovered several bugs in the ASIC code that were not found by ASIC verification test benches. Show less

Rtp, Nc

Analog Modem Module, 2 Ports – Replaced an older analog modem module used for modem pools, remote access to router, and backup WAN interfaces. Rewrote key parts of the device driver to stabilize the call setups, and provided needed changes for the new analog modem.• During thorough testing, found and fixed a major flow-control bug, which provided a reliable backup WAN and saved a large customer account. The account was undergoing a major infrastructure change, resulting in… Show more Analog Modem Module, 2 Ports – Replaced an older analog modem module used for modem pools, remote access to router, and backup WAN interfaces. Rewrote key parts of the device driver to stabilize the call setups, and provided needed changes for the new analog modem.• During thorough testing, found and fixed a major flow-control bug, which provided a reliable backup WAN and saved a large customer account. The account was undergoing a major infrastructure change, resulting in multi-million dollar sales of Cisco equipment. Earned a company award for these efforts.• The improved, more robust analog modem has been used in subsequent products and has increased sales for this major account, as well as other Cisco client accounts.Analog Modem Module, 16 Ports – Took ownership of software development after two software engineers left mid-project. The module included a PPC CPU and firmware to manage a 16-port analog modem module.• Supported project through dev-test which required fixing bugs found by dev-test group.• Found and fixed a major software design flaw that caused a race condition. The fix resolved unexplained intermittent call setup failures.E1T1 Module – Ported firmware for E1T1 framers from a PPC CPU to a Motorola CPU. Created a Read-Only (code) and a Read-Write (data) section in the SRAM by using two of the CPU’s chip-select lines combined in the FPGA into a single chip-select line for the SRAM. Initialized the CPU code section with an illegal op code to more easily detect an errant CPU.GigE Interface Module – Wrote new core diagnostic code to test the FPGA design and created a state machine to enable easy modification of the JTAG handshake sequence. The code has been reused to test later hardware modules.• Enhanced existing diagnostic code by enabling multi-queue channel support.• Fixed day-one bugs in the channel setup sequence, and corrected many coding standard violations that had caused multiple run-time crashes. Show less

Rtp, Nc

Maintained the LAN Emulation Client (LEC) as part of LAN Emulation (LANE) protocol over ATM. Updated the LEC code base to support newer IETF standards. Provided customer support to solve various problems with LANE ATM products.

Herndon, Virginia

Designed a routing protocol manager. Coded the virtual connection manager to maintain data and control plane connections.

Gaithersburg, Maryland

Project leader of Penril’s Virtual Circuit eXchange (VCX) group. The VCX, the company’s top income producer, is a family of statistical multiplexors based on the Motorola 68000 and 68302. Designed a flash program routine and boot block code, modified an asynchronous device driver, made operating system changes, and added a feature to copy the operating system to RAM for the VCX250. Added a multiple session feature that allows up to eight concurrent sessions per asynchronous port.

Reston, Virginia

Major contributions included designing firmware for an Intel-based communications interface board, communications software for a DOS PC, and user interface and data management software for an industrial control supervisory computer.

Easley, South Carolina

Designed a microcontroller card for use in a variety of industrial machines in both master/slave and stand-alone configurations. This card included an 8051 microcontroller and various industrial controls. Created a real-time task switcher that allows up to four tasks to run concurrently on the 8051.