Dayanand Paramane Email & Phone Number

Irvine, CA

DFT for RF dominated SoCs with tuners, complex digital filters etc.

Orange County, California Area

Hands on design execution on multiple fronts like Defining DFT specs, partitioning, implementation, defining Quality/Production/Test program, verification, timing closure in DFT modes. Interfacing cross functional teams like Physical Design, AMS IP vendors, RTL Design, Verification, Product and Test Engineering on multiple aspects during ASIC design process.

Hyderabad Area, India

Design execution SoC implementation, timing closure, DFT architecture, implementation, verification etc. Development boot code for soft repairs, selftest; Also handled functional mode timing closure with critical high speed interface modules like Serdes.

Bangalore, India

DFT Architecture and implementation, DFT Methodology Improvements

Pune Area, India

Managing team of DFT Engineers working multi-site for projects from different Business Units. Defining and implementing DFT Architecture for ASICs with different complexities. Improvement in the methodology to adopt best implementation practices. Working with Test Engineers for defining the test program, bringing up vectors, Post silicon activities.

Pune Area, India

RTL Design, integration, TB development, verification, and SOC Implementation, Defining the specifications for different sub-modules, Architecting the clocking for the chip, RTL Design and coding of individual modules, Integration of modules and validation, Synthesis and Static Timing Analysis, Gate level Simulations with timings, Toggle rate report.

FPGA based digital logic implementation for fibre optic communication, signal correlator systems, Ethernet MAC etc.