Debashish Bhattacharjee Email & Phone Number

Santa Clara, Ca, Us

Product Definition Owner for Data Center, CPU and Tegra products

Santa Clara, California, Us

- Own and define bounding box limits and maximize performance for the given power and thermal envelope while meeting projected yield requirements for industry-leading 7nm and 5nm Data Center GPU products- Enable per part voltage-frequency curve, derive droop voltage model, and guardband by characterizing silicon at both ATE and SLT- Managed multiple phases of NPI: Drive project schedules, identify product requirements and dependencies, define characterization and test plan, integration, ramp to volume testing- Analyzed large volume of data to drive business decisions, used statistical analysis techniques and visualization tool to present findings to the engineers, architects, and the senior management (Directors/VPs)- Developed complex regression models that predicts GPU performance, power, yield trade-offs. Defined best practices and improvements, which are emulated on other projects- Led and debugged multiple issues impacting time to market, yield, and performance distributionKey Projects: 1) Designed die grouping strategy of the most expensive and complex chiplet products AMD designed till date2) Implemented dynamic per part Vmin model, which leads to 6% power savings3) Developed python scripts to automate parametric correlation studySkills:- JMP, MYSQL, Python, Microsoft Office Suite- Hands-on experience in Verigy93k

Malta, Ny, Us

- Responsible for weekly reviews with the customers and management, driving a team towards achieving quarterly wafer yield targets by systematically driving down yield issues- Identify the key Defect of Interest (DOI) and collaborate with different process modules to design experiments and improvement plans to reduce wafer defects- Led Statistical Process Control (SPC) team and was accountable for monitoring defect excursion through Health of the line (HOL) and SPC charts- Spearheaded cost reduction projects and collaborated with the cross-functional team to implement several automation projects- Mentored new engineers, interns, technicians by arranging training and workshops to ensure proper knowledge transferKey Projects: 1) Automated YDD SPC DOI platform, which is capable to sort DOI charts based on the technology node and set an automated control limit based on a set of criteria. This project was recognized to save 16 engineering hours per day2) As a team leader of 40nm low power yield improvement team, our department achieved the aggressive yield target of the biggest 40nm customer within one year

Malta, Ny, Us

- Responsible for analyzing inline defect information and maintaining worldwide benchmark sensitivities for defect detection- Design, execute and analyze partition studies for defect source identification and defect reduction to drive continuous yield improvement - Perform root cause analysis of excursion events and inform cross-functional team to take corrective and preventive action on tool/process recipe Key Projects:1) Led the SRAM task force team and improved 40nm low power SRAM yield by 1.1% within six months2) Established defect library for technicians, which improved defect reclassification rate by 10%

Master Of Science (M.Sc.), Electrical Engineering, Specialization In Microelectronics

Bachelor Of Science (B.Sc.), Electrical And Electronics Engineering