Versal QEMU Co-simulation - Used Xilinx System Debugger (XSDB) to connect to GDB (GNU Project Debugger) server and interface with both the hardened Processing System (PS) and IP instantiated in the Programmable Logic (PL) - Automated the Vivado/Vitis build flow to generate the required support files to enable the co-simulation flow - Successfully emulated the Zynq UltraScale+ RFSoC DFE post-silicon Validation - Used to emulate IP currently under developmentLab Equipment Management - Drove process improvements for the management of equipment inventory & calibration - Managed first on-site visit from Rohde & Schwarz to calibrate high end RF test & measurement equipment

COVID-19 Lab Automation - Drove processes to define & implement a remote working environment which minimized on-site human interaction during the COVID-19 pandemic & beyond - Coordinated with IT, Facilities & Engineering to develop an infrastructure which allowed for remote monitoring of all bench equipment, as well as power cycling and high resolution camera accessZynq UltraScale+ RFSoC DFE Post-silicon Validation - Defined & implemented a SW solution on Arm Cortex A53 to test DFE hard IP in conjunction with soft IP in FPGA programmable logic - Used Vivado & Vitis to generate bitstream & elf collateral - Used emulation to test validation flow in advance of initial siliconVersal SysMon Digital Design Implementation & Post-silicon Validation Owner - Created digital design implementation document based on high level architecture specifications - Verilog, synthesis, P&R, STA - Top level block integration - Gatekeeper for QOR of IP delivered to integration team incl: linting, CDC, equivalence checking - Drove definition for digital testing of initial silicon - Led initial post-silicon ES validation using Vivado, Vitis & Labview/TestStandUltrascale+ System Monitor Design & Post-silicon Validation (16nm) - Verilog, synthesis, P&R, STA - Top level block integration - Gatekeeper for QOR of IP delivered to integration team incl: linting, CDC, equivalence checking, - Drove definition for digital testing of initial silicon - Led initial post-silicon ES validation using Vivado & LabviewUltrascale System Post-silicon Validation (20nm) - Contributed to definition of digital testing for initial silicon - Contributed to initial post-silicon ES validation using Vivado & Labview

Ultrascale System Monitor Design (20nm) - Verilog, synthesis, P&R, STA - Top level block integration - Gatekeeper for QOR of IP delivered to integration teamSpartan 6 IOI Design & Post-silicon ValidationSpartan 3E Digital Clock Manager (90nm) - Verilog, synthesis, P&R

Spartan 3 Digital Clock Manager (90nm) - Verilog, synthesis, P&R