Deepak Singh Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

1. Integrated FPGA with DAC/ADC chip using JESD204B protocol (RTL level) for high speed data transfer involving transport and PHY layer ( SerDes).2. Implemented RTL Design for SFO/SPO (Sampling Frequency Offset/Sampling Phase Offset) correction using RRC filter, Interpolator, Gardner and PI Controller blocks.3. Implemented RTL Design for clock recovery mechanism using inbuilt CDR circuit.4. Implemented SyncE (Synchronous Ethernet) using Skylabs Si5328 for cleaning of recovered clock as per ITU-T standards leading to Synchronous Network Operation.

India

• Designed a 1X3 Router using Verilog and verified it using System Verilog (UVM).• Verified AHB-to-APB bridge using System Verilog (UVM).• Developed strong skills in VLSI design and verification techniques.

Bengaluru, Karnataka, India

• Trained Indian Air Force personnel on cutting-edge Ground/ Airborne Radar systems• Developed and implemented customized training programs for optimal learning outcomes• Conducted assessments to measure knowledge retention and skill proficiency

. Strong troubleshooting and analytical skills using lab equipment including oscilloscopes/spectrum analysers.• Managed fault rectification processes of ground and airborne Radar systems ensuring state-of-the-art radar systems were operational.• Collaborated with cross-functional teams to troubleshoot and resolve radar system issues efficiently.

Master Of Technology (M.Tech.), Vlsi Design, First Division With Honours/ 81%

Cmos Digital Vlsi Design, Electrical, Electronics And Communications Engineering, 78%

Elite + Silver certificate

Nptel Course, Introduction To Research, 79%

Elite certificate

Bachelor Of Engineering, Electronics And Communication, First

First