Hands-on Proficiency in RTL Design and Development for complex blocks of an SOC and Subsystems Integration Using VHDL.• Full understanding of VLSI Design Methodologies and tools including VHDL, Verilog, Simulation, Synthesis and Formal Verification.• Familiar in Programming Languages like VHDL, Verilog and System Verilog. • Knowledge of FPGA architecture and IO Constraints.• Hands-on Proficiency in IP Design and Development.• Worked in Clock domains Crossings and Timing analysis.• Familiar with FPGA Xilinx Zynq SoC, Spartan 6 and Artix 7.• Protocols: AXI• Experience in SOC Interconnect protocols like AXI.• Communication protocols including I2C, SPI, USART, UART, MDIO.• Experience in PCI Express and Ethernet Protocols.• Excellent logic design concepts.• Excellent Verification concepts.• Experience in control path-oriented designs like asynchronous FIFO, DMAarchitecture, Shared Memory interface design.• Experience in creating code coverage and functional coverage plans and reports.• Experience with tools like VIVADO, SDK, ModelSim, Questasim, Cadence Encounter RTL Compiler.• Good hands on with Logic Analyzer and Digital Signal Oscilloscopes.• Good hands on with Function generator, Multimeter and hardware components.• Good hands on with real time verification of RTL Codes with Hardware.• Excellent knowledge of Linux.• Experience with automation using scripting techniques such as MATLAB ScriptAnd Basic knowledge in Python Script.• Experience in automation tools like MATLAB, Python (Basic).• Good C, Embedded C programming skills, analytical, debugging and Problem Solving skills. • Experience with tools like Keil, LPCXpresso. • Familiar with Microcontrollers and Microprocessores like 8051, ARM cortex M0+, LPC2378, LPC2364.• Basic knowledge in Tools like Proteus, Scilab, and PSpice.• Basic Programming skills in C++, Data structures, Assembly language