• Experience in analog, and digital layout design in (FinFET) 7nm,16nm, 28nm, 90nm and 500nm Technology nodes.• EDA tool experience in Cadence - Virtuoso & Assura; Calibre RVE and Synopsys - Custom Compiler & IC Validator• Involved in floorplan, placement and routing and characterizations like DRC, LVS, ERC • Design of standard cells and Analog blocks like LDO, BGR, PLL etc developed• Good understanding on layout dependent effect, Matching and shielding, Latchup, EM IR, Antenna • Involved in full chip optimization of floorplan and placement and top level implementation• Understanding of memory architecture types and routing constraintsProjects:- Standard cell Layout of Digital Gates- Comparator- IBIAS- Single Stage and Double stage OpAmp- SAR ADC-Band Gap Reference- Low Drop-out Regulator circuit- Phase Locked Loop (PLL)- LED DriverSubjects of interest:- Fabrication process- Semiconductor Physics- Electronic devicesExperience:- Layout design- MG-Si, Polysilicon, Ingots, Wafers, Cells and Module Manufacturing.- Fabrication of Nanofibers.- Electrospinning process.