Daniel Kucharski Email & Phone Number

Camarillo, Ca, Us

Architecture and design of 100G, 200G, and 400G Telecom and Datacom transceivers and SerDes products.

Carlsbad, Ca, Us

Technical lead for analog and high-speed design team. Responsible for specifications, architecture definition, system modeling, circuit design, verification (including top-level in AMS), signal integrity analysis (including EM modeling in HFSS), functional testing, and related documentation. Designed low-power 10Gb/s and 14Gb/s integrated optical receivers and MZI-based transmitters in 0.13µm CMOS photonics technology for QDR and FDR active optical cable products. Proposed and developed architecture and circuits for 25Gb/s optical transceiver. Led a team to develop a 10Gb/s CDR. Defined and verified CDR and PLL architecture, including behavioral modeling in Verilog-A. Designed phase detector, charge pump, and 10GHz VCO. Assigned and supervised design, layout, and verification tasks. Completed top-level functional verification of the CDR in UltraSim. Pioneered integrated optoelectronic modeling flow in Cadence to enable joint simulations of optics and electronics. Involved in device modeling and PDK enhancements. Contributor to IC failure analysis work.Related Publications:D. Kucharski et al., “10-Gb/s 15-mW Optical Receiver with Integrated Germanium Photodetector and Hybrid Inductor Peaking in 0.13-µm SOI CMOS Technology,” ISSCC 2010 Dig. Tech. Papers, pp. 360-361, Feb. 2010.A. Narasimha et al., “A Fully Integrated 4×10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology,” IEEE J. of Solid-State Circuits, vol. 42, no. 12, pp. 2736-2744, Dec. 2007.B. Analui, D. Guckenberger, D. Kucharski, and A. Narasimha, “A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-µm CMOS SOI Technology,” IEEE J. of Solid-State Circuits, vol. 41, no. 12, pp. 2945-2955, Dec. 2006.

Ithaca, Ny, Us

Developed a set of low-voltage circuit topologies and demonstrated them in a variety SiGe BiCMOS telecom circuits, including 43-45Gb/s CDR, 50Gb/s PRBS generator, 40GHz prescaler, and 10Gb/s AGC amplifier. Researched and implemented area-efficient bandwidth extension techniques.Related Publications:D. Kucharski and K. Kornegay, “2.5 V 43-45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family,” IEEE J. of Solid-State Circuits, vol. 41, no. 11, pp. 2154-2165, Sep. 2006.D. Kucharski and K. Kornegay, "A 43-45Gb/s 2.5V Integrated Clock and Data Recovery Circuit in SiGe Using Low-Voltage Topologies," Proc. BCTM 2005, pp. 86-89, Oct. 2005.D. Kucharski and K. Kornegay, "A 40GHz 2.1V Static Frequency Divider in SiGe Using a Low-Voltage Latch Topology," RFIC Dig. Tech. Papers, pp. 461-464, June 2005.D. Kucharski and K. Kornegay, "A 40Gb/s 2.5V 2^7-1 PRBS Generator in SiGe Using a Low-Voltage Logic Family," ISSCC 2005 Dig. Tech. Papers, pp. 340-341, Feb. 2005.D. Kucharski and K. Kornegay, "Jitter Considerations in the Design of a 10Gb/s Automatic Gain Control Amplifier," IEEE Trans. Microwave Theory and Techniques, vol. 53, no. 2, pp. 590-597, Feb. 2005.D. Kucharski and K. Kornegay, "A Low-Power 10Gb/s AGC Optical Postamplifier in SiGe," RFIC 2004 Dig. Tech. Papers, pp. 25-28, June 2004.

Designed, tested, and characterized 20Gb/s per channel 4×12 VCSEL driver array in 0.13μm CMOS for a Tb/s data link sponsored by DARPA (a.k.a. Terabus). The driver incorporates a novel pre-emphasis circuit, which enables 20Gb/s operation from a 10Gb/s laser. It was the fastest VCSEL-based optical transmitter at that time. Developed a novel output stage topology to improve optical modulation amplitude.Related Publications:D. Guckenberger, J. Schaub, D. Kucharski, and K. Kornegay, "1V, 10mW, 10Gb/s CMOS Optical Receiver Front-End," RFIC 2005 Dig. Tech. Papers, June 2005.D. Kucharski et al. "A 20Gb/s VCSEL Driver with Pre-Emphasis and Regulated Output Impedance in 0.13μm CMOS," ISSCC 2005 Dig. Tech. Papers, pp. 222-223, Feb. 2005. D. Kuchta et al., "120Gb/s VCSEL-Based Parallel Optical Link and Custom 120Gb/s Testing Station," J. Lightwave Technology, vol. 22, pp. 2200-2212, Sep. 2004.

Responsible for transistor-level design, layout, and verification of CMOS ASIC library elements including high-speed logic gates and I/O circuits.

M.S. And Ph.D., Electrical Engineering

M.S. Program, Electrical Engineering

B.S., Electrical Engineering