Daniel M. Email & Phone Number

Redmond, Washington, Us

- Develop and support custom clocking methodologies in both Fusion Compiler and Innovus for high-performance clock distributions in large chip subsystems, while working closely with macro owners, logic designers and vendors- Implement, analyze and tune clock trees for low skew and balanced transition times- Mentor new engineers on best practices

San Diego, Ca, Us

- Automated clock construction flow to allow macro designers to run independently, requiring less clock team resource- Led project teams of 2-5 engineers to ensure clocks were skew-balanced across 10+ unique hard macros, while meeting aggressive performance and schedule targets- Collaborated with logic designers, macro owners, and library developers to solve complex placement, routing, and timing challenges- Trained new team members in design flow execution and best practices, enabling rapid contribution to team objectives- Interfaced with EDA software vendors to influence development and enhancement of tool features for improved analysis of clock performance and reduced power and turnaround time

Armonk, New York, Ny, Us

- Transitioned worldwide ASIC design centers from silicon-dominated, non-uniform clock tree insertion methodology to balanced, uniform tree style to minimize process variation effects- Developed, released, and supported methodologies for routing high-performance clock distributions on ASICs and microprocessors- Developed and released methodology for automating physical design of balanced test clock distributions, increasing tester throughput and reducing overall testing expense- Interlocked closely with other developers in logic, floorplanning, timing, and physical design disciplines- Educated and supported IBM and third-party designers across multiple geographies- Trained and mentored new team members in North America and Asia

Armonk, New York, Ny, Us

- Performed floorplanning and physical design (placement-driven synthesis, routing, timing closure) on two hierarchical units of a microprocessor- Ran DRC and implemented necessary design fixes- Constructed and routed high-performance clock grid designs, including placement, wiring, wire tuning, and simulation

Armonk, New York, Ny, Us

- Led multi-site engineering team responsible for delivering leading-edge ASIC clocking methodology using tools developed internally and through partnership with University of Bonn, Germany- Developed and patented Structured Clock Buffer (SCB) placement and routing methodology for minimizing clock skew and process variation effects in ASIC clock trees, enabling higher-frequency ASIC designs with reduced timing closure effort

Armonk, New York, Ny, Us

- Developed graphical interface for bitstacking placement tool to improve ASIC designers' productivity