Dmitry Golubkov Email & Phone Number

Санкт-Петербург, Россия

Эспоо, Уусимаа, Финляндия

• Project: MEMS-based oscillators and clock generatorsMember of a CMOS team. Involved in RTL design of single digital blocks and verification of digital and entire digital+analog parts of the chip
• Designed RTL for OTP memory control unit, rd/wr interfaces, test output interface and other RTL components (CRC, ECC, control FSMs).
• Developed Verilog behavioral models for analog components (Voltage regulators, VCO, etc.) to be used during verification
• Developed testbeches and tests to simulate digital part of the design with analog units presented as Verilog models (using Verilog, C++, PLI)
• Developed verification environment for regression testing (using Perl, Python)
• Performed trial synthesis for area estimations

Санкт-Петербург, Санкт-Петербург, Россия

• Project: FPGA based H264 Encoder/DecoderMember of FPGA team to implement H264 Encoder/Decoder FPGA prototype for real time video stream encoding and decoding. Responsible for verification and RTL design.
• Developed verification environment for multi-thread regression testing in ModelSim. (using SystemC, Perl, TCL)
• Integrated C++ encoder/decoder model into testbench to generate input stimulus and "golden" result. (using Verilog, SystemVerilog, SystemC)
• Performed CPU integration into design and was involved in CPU firmware debugging (open source 32bit MIPS CPU core “Plasma”)
• Designed 64bit arithmetic accelerator for 32bit CPU core with optimization for Xilinx Virtex 6 (using DSP48E1).
• Designed Verilog interconnection blocks for Altera Avalon, AMBA AHB.

Санкт-Петербург, Санкт-Петербург, Россия

• Undergraduate Technical InternMember of the hardware-design team. Part-time position as an intern and student. Involved in verification, debugging and RTL design. Project: Data-streaming accelerator
• Designed VHDL block for data exchange between the accelerator and Altera NIOS CPUProject: FPGA implementation of image-recognition algorithm SURF
• Designed VHDL block for DVI frame detection and data decoding.
• Designed software I2C controller for ARC CPU (using C++).
• Performed ARC CPU firmware testing
• Involved in debugging of Altera Stratix IV FPGA prototype Project: Multi-port memory interconnection system