Eric Gonzales Email and Phone Number
Intel Corporation Austin, TX Jun 2012-PresentAs a seasoned Design Verification Engineer at Intel Corporation, I bring over a decade of experience in the semiconductor industry. My strength lies in formulating and executing verification strategies for complex design IPs and CPUs, working closely with architecture and design engineers to identify verification test scenarios.My proficiency in SystemVerilog and UVM has allowed me to construct and enhance constrained-random verification environments. My understanding of SVA and leading formal tools has been vital in formally verifying designs. I have showcased my ability to create comprehensive testbenches, encompassing UVM agents, interfaces, coverage, and components, thereby ensuring precise design functionality. My skills in scripting languages such as Python and Perl have been instrumental in automating inefficient processes, leading to significant time savings.My broad experience with CPU architectures, coupled with my expertise in debugging across simulation, emulation, and post-silicon environments, has made me a versatile engineer, crucial in delivering functionally accurate designs. I have a proven history of identifying and writing functional coverage for stimulus and corner cases, successfully meeting tape-out requirements.I have been acknowledged for my exceptional contributions throughout my career, including the prestigious 100+ RTL Bug Club recognition in 2019 for identifying a total of 142 RTL bugs, and the esteemed 2013 Q2 AVE Excellence Award for exemplary planning, execution, and debug of Silvermont Thermal and LTEC features.As a highly motivated and results-focused engineer, I excel in collaborative, cross-functional teams and am constantly seeking opportunities to drive innovation and excellence in the semiconductor industry.
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Cpu Design Verification Engineering ManagerIntel Corporation Nov 2024 - PresentAustin, Texas, United States -
Senior Cpu Design Verification EngineerIntel Corporation Feb 2020 - PresentAustin, Texas, United StatesHighly recognized within the Atom Organization for exceptional contributions in conceiving, developing, and implementing the testbench components necessary for the verification of the Atom CPU.Serve as the lead verification engineer for the Exec verification team where I have demonstrated strong leadership and ensured the robustness and functionality of the Allocation, Scheduling, Executing, and Retiring partitions of the Atom CPU.Proficiently utilize object-oriented programming (OOP) and universal verification methodology (UVM) to create robust System Verilog (SV) assertions, guaranteeing thorough validation of system behavior and adherence to design expectations.Leverage my expertise in Perl and Python to develop efficient SV transactors, enabling comprehensive verification of system functionality and enhancing problem-solving capabilities.Conduct thorough root cause analysis and utilize code coverage techniques to maintain the highest quality standards in design verification.Known for excellent communication skills, effectively collaborating with cross-functional teams and stakeholders.Demonstrated leadership qualities in guiding and mentoring junior verification engineers.
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Dft Design Verification EngineerIntel Corporation Apr 2016 - Feb 2020Austin, Texas, United StatesLed the verification of a broad spectrum of features including cluster-level arrays and memories, In-Die Process Variation (IDV), Digital View Pins, IEEE1149.1 Joint Test Access Group (JTAG) FSM & Instruction/Data Register, Soft IP (SIP), Duty Cycle Detector/Corrector, PLL & Thermal IP, Access Mechanisms, and Probe Mode.Skillfully applied DFX (Design for Excellence) and DFT (Design for Testability) strategies, along with JTAG and Automated Test Generator Patterns (ATPG) techniques. This approach enabled the detection and correction of various silicon faults, ensuring comprehensive functional coverage through directed test based testing.Closely collaborated with post-silicon teams, providing my expertise in debugging Scan, Array validation, and other DFX/DFT related activities.Received the prestigious 100+ RTL Bug Club recognition in 2019 for having identified a total of 142 RTL bugs.My expertise in object-oriented programming (OOP) and universal verification methodology (UVM) with SystemVerilog was crucial in building robust verification environments. This ensured thorough design verification, particularly in creating testbenches in UVM format.Used Perl and Python to develop efficient verification scripts, enhancing problem-solving capabilities and contributing to successful root cause analysis.Upheld the highest quality standards in design verification by having employed functional coverage through directed test based testing.My excellent communication skills were instrumental in effectively conveying complex technical information and collaborating with cross-functional teams.Showcased strong leadership abilities, guiding and mentoring team members to achieve project success and meet verification goals.
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Cpu Validation EngineerIntel Corporation Sep 2014 - Apr 2016Austin, Texas, United StatesDemonstrated exceptional problem-solving skills and performed root cause analysis, contributing to the identification and resolution of critical issues.Was responsible for analyzing test results and debugging failures. This involved running test regressions and debugging failing tests to isolate and root cause failures.Utilized various hardware and software tools for debugging and proposed methodology and technical solutions to enhance the validation process.My excellent communication skills were instrumental in effectively conveying complex technical information and collaborating with cross-functional teams.Showcased strong leadership abilities, guiding and mentoring team members to achieve project success and meet validation goals.This experience equipped me with a deep understanding of CPU validation processes and the ability to navigate the unique challenges of post-silicon environments. My technical expertise, problem-solving abilities, and leadership skills were key to my success in this role.
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System Validation EngineerIntel Corporation Jul 2012 - Sep 2014Austin, Texas, United StatesLed CPU Scan Chain validation efforts, developed robust debug and survivability scripts, and achieved core bring-up during Power-On events. Won the 2013 Q2 AVE Excellence Award for planning, executing, and debugging Silvermont Thermal and LTEC features, resolving 23 critical bugs despite Valleyview's delayed enablement.Created a configurable automation framework for the PPT Validation Group, reducing initial setup and run phases by 80%.Applied analytical skills and DFX, DFT, and JTAG expertise to validate computer systems.Used object-oriented programming (OOP) and Python scripting to create efficient test content generators for post-silicon validation.Presented at Intel's Software Professionals Conference on topics like "Scalable, Configurable Automation Framework for Core Power, Performance, and Thermal Validation" and "Effective Test Content Generator for Post Silicon Validation."
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Project ManagerAir Force Civil Engineer Center Mar 2009 - Jul 2012San Antonio, Texas, United StatesLed the successful management of a diverse portfolio of military construction projects totaling over $20 million, spanning military installations in Texas, Alaska, and Nebraska.Collaborated closely with stakeholders to define project requirements, advocate for funding, and devise optimal contract strategies.Developed and disseminated comprehensive acquisition schedules, ensuring stakeholders and customers remained well-informed of project progress.Maintained vigilant oversight of contractor performance, encompassing quality control, adherence to schedule, cost management, and processing requests for variances.Assessed and approved contractor-submitted vouchers, validating achieved milestones and completed work for accurate and timely payment.Fostered effective cooperation with internal AFCEC functions, ensuring seamless coordination for timely acquisition awards.Recognized for outstanding performance, receiving the Civilian Performance Award for Q3 2010 and being honored as Employee of the Quarter.
Eric Gonzales Education Details
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Computer Engineering -
Electrical Engineering
Frequently Asked Questions about Eric Gonzales
What company does Eric Gonzales work for?
Eric Gonzales works for Intel Corporation
What is Eric Gonzales's role at the current company?
Eric Gonzales's current role is CPU Design Verification Engineering Manager at Intel | CPU DV | DFT DV | CPU Val | PM.
What schools did Eric Gonzales attend?
Eric Gonzales attended The University Of Texas At San Antonio, The University Of Texas At San Antonio.
Who are Eric Gonzales's colleagues?
Eric Gonzales's colleagues are Arthi Danabal, Daniel Schmidt, Richard Sande, Lâm Thị Tiền, Laura Devany Grow, Jennifer Mick, محسن البدري.
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