Eric A. Email & Phone Number

Rochester, Minnesota, United States

Rochester, Minnesota Area

I work with individuals out in the Rochester community as a coach, mentor and supervisor in a light industrial work environment.

Rochester, Minnesota Area

Meat clerk role directly serving the customer through delivery and creation of products.

Rochester, Minnesota Area

ASIC Design Center Engineer. Activities consist of DFT insertion, boolean equivalency flow development and other design automation work. Owner and developer of boolean equivalency process and scripts for the design center. Main focal point for questions regarding the tool flow and additional internal support point of contact for Cadence Confromal.If you are a student, please see http://globalfoundries.com/about/careers/opportunities-in-the-us for GlobalFoundries opportunities.

Rochester, Minnesota Area

Position has included work on IBM Research ASICs (32nm IBM Technology) and IBM Design Center ASICs (32nm IBM Technology) covering process flow for DFT structures. Tasks include: DFT insertion, DFT process customization, CMOS checks resolution and boolean equivalency checking.I'm have worked on a networking 32nm ASIC and an IBM Research 45nm ASIC design. Tasks include: Chip integration, customer issue resolution, IBM DFT insertion, boolean equivalency verification and process flow.

Rochester, Minnesota Area

Internal IBM and external customer support providing design consulting services ranging from FEP, test, timing closure consultation to timing closure solutions. Current projects have revolved around ownership and resolution of customer netlist Memory BIST insertion, FEP, CMOS check issue resolution, test structure verification, test timing closure, boolean equivalency process definition and checks, and physical design issues as they pertain to manufacturing test. These netlists consist of large 32nm, 50M gate ASIC designs.I also lead a team of FEP engineers who perform the above tasks. As a leader and resource, I also have been using my broad experiences to teach these engineers on the FEP (45nm and 32nm technologies) flow in IBM ASICs. Outside of the area, I have been using my experiences to provide learning and tools to other IBM engineers.

Rochester, Minnesota Area

Logic integration/Implementation engineer taking FCAL and SAS host interface VHDL ASIC designs through chip integration, clock structure design, integration of logical clocking structures, timing closure, manufacturing IBM DFT, and CMOS checking. I regularly interacted with the timing closure and physical design teams to ensure logic designs met the needs of the back end teams.

Rochester, Minnesota Area

Provided timing tool support, system level ASIC interconnect signal integrity analysis, clock VHDL design, semi-custom and ASIC physical design along with timing closure.From January 1999 through December 2002, I worked in the IBM Storage Division performing server class HDD logic integration, synthesis, clocking, timing, DFT and netlist checking closure for FCAL and SAS designs.

Camden, Nj

Worked with various Lockheed sites on boolean verification.

Associate Of Arts And Sciences - Aas, Network And System Administration/Administrator, 4.00

Completed an A.A.S. in I/T Network Administration. Security coursework has included: Computer security, network security and firewalls.

Computer Networking / Cisco Networking

Activities and Societies: AITPCoursework included: Cisco Networking, Switches & Routers, Scaling Networks and WAN Interconnected Networks.

M.S., Electrical Engineering

B.S., Computer Engineering

Activities and Societies: Graduated With Distinction, Eta Kappa Nu, Tau Beta Pi, Upsilon Pi Epsilon, IEEE