I have completed an I/T A.A.S in Network Administration from Dakota County Technical College.I just started a new position at Ability Building Community as a Training Specialist.Past career experience - In the most recent past, I was a job coach at ABC working with individuals out in the Rochester community. My role was one of coach, mentor as well as role as a supervisor. I was working in a light industrial environment with these individuals.As a former engineer, I have experience as a design engineer working with ASICs and semi-custom chip development methodologies. Recent work has consisted of insertion of IBM/GlobalFoundries DFT structures and insertion of post-synthesis custom requirements through scripted (Tcl, Perl, ksh, etc) design alterations, CMOS checks issue resolution and boolean equivalency checking.I was the owner of the boolean equivalency checking scripts and process along with co-developer of the methodology. Additionally, I served as the internal point-of-contact for the process flow and issue resolution that arose during fellow engineers use of the equivalency tool.I have broad knowledge across ASIC chip development including the above areas as well as design languages (VHDL/Verilog), timing closure, test structure verification and physical design. I have experience in synthesis, timing, DFT insertion, test, engineering change (EC) generation and verification, boolean equivalency checking and some physical design. I regularly work with programming languages (Perl, Tcl), Unix/Linux shell scripting (ksh, csh) to develop improved methodology and process flows, augment EDA tools, improve design quality and reduce design time.Career broad level of experience: HDL design, clock logic design, timing closure, synthesis, IBM/GlobalFoundries manufacturing test structure insertion, test structure verification, boolean equivalency checking, methodology and ASIC process development.