As an aspiring VLSI circuit designer, I am pursuing a Master of Science in Electrical Engineering at the University of Southern California, where I have gained a solid academic foundation in digital design, computer algorithms, and VLSI courses. I have also engaged in hands-on projects involving the Tomasolu Processor, RISC-V Processor, PCIe, and NetFPGA-based Hardware Accelerators, demonstrating my proficiency in Verilog, ModelSim, and Cadence tools. In addition to my academic achievements, I have also gained valuable industry experience as a Hardware Development Engineer at Suzhou ETRON Technologies Co.,Ltd, where I developed the circuit test application using PyQt5, conducted schematic and PCB design, and debugged hardware designs with Chipscope. Furthermore, I have published a journal as the first author and filed a patent based on my research on acoustic analysis and signal processing using Python and CNN at Xi'an Jiaotong-Liverpool University. I am actively seeking entry-level full-time opportunities in the RTL/DV/PD domain, where I can apply my skills and knowledge in VLSI circuit design and testing, and contribute to innovative and cutting-edge solutions. I am eager to learn from and collaborate with experienced professionals, and to grow as an engineer and a leader. Please feel free to contact me if you are interested in my profile.