Design Verification Team Supervisor
CurrentI lead a fantastic team of design verification engineers in verifying complex RISC-V RTL designs, utilizing cutting-edge methodologies and tools. Our primary focus is on employing advanced verification techniques such as Universal Verification Methodology (UVM), and hybrid verification techniques to ensure robust testbench development and verification coverage. Leveraging SystemC and SystemVerilog, we utilize co-simulation to ensure comprehensive coverage and reliability of the designs.One of my key responsibilities is planning and executing verification strategies, from concept to final sign-off. This includes RTL testbench automation, RTL design verification, and scripting for regression testing, test creation, debugging, and coverage analysis. I actively contribute to research and the development of innovative verification methodologies, ensuring that my processes remain at the forefront of the industry. By staying current with the latest trends and continuously refining my techniques, I drive efficiency and precision in verifying complex hardware systems.I have expertise in cache coherency, cache management, and the verification of complex subsystems like set-associative caches with features such as write-back and write-allocate policies.I also have a good understanding of hardware security and currently contributing to several publications and projects related to verification and RISC-V architecture design. My skills include using Synopsys tools, Verdi, and Linux for simulation and debugging, allowing for precise and efficient verification.Beyond technical execution, I’m committed to promoting a culture of self-development and motivation within the team. I regularly conduct employee training sessions, helping team members improve their skills in areas such as creative problem-solving, technical mastery, and personal growth. As a leader, I focus on fostering a positive work environment, driving both team and individual success.
