I work on the Shader Compiler for the AMD Radion graphics processor

IBM/Rational Software (IBM acquired Rational 03/2003) Worked on Purify, Quantify, and PureCoverage products.Purify is a debugging tool for C/C++ programmers. It detects memory leaks, un-initialized memory reads, array bounds violations and other errorsQuantify is a performance profiler for C/C++ programmers.PureCoverage is a code test coverage analyzer for C/C++ programmers.They all share a common code base, mostly in C++ with C for the runtime library.The unique part of these tools is that they work using a technique known as Object Code Insertion (OCI).The OCI engine takes in object code, disassembles it, add more code, and writes it back out.This engine is just like a compiler, except that it takes in object code, rather than source code.My responsibility, for the last 13 years, has been to implement support for new platforms. That requires me to retarget the engine, rewrite the assembly code in the runtime library, and port the rest of the code base.I did that for 7 new platforms: sparc64/solaris, pa64/hp-ux, x86/linux, amd64/linux,x86/solaris, amd64/solaris, and ia64/windows.; The ia64 project took 3 of the 13 years, since it required a complete rewrite of the OCI engine, from scratch, using C++, rather than a retarget of the existing C engine.I also converted many of the other engines from C to C++.My most recent work has been to add support for Intel AVX to our x86/amd64 engine and add Power6 and Power7 support to our PowerPC engine.

Worked on StrongARM1500 and EV-7 Alpha Products.StrongARM1500 is a multimedia-enhanced version of the ARM architecture. I wrote a complete Macro Assembler, and a performance simulator/emulator for the chip, in C, both from scratch.EV-7 Alpha is a high performance 64 bit processor. I ran performance simulations, using spec95, to assist in design tradeoff analysis. I also contributed to the design of the on chip memory controller, which directly controlled RDRAM.

Worked on MrPlus and MrCppp products. MrPlus is a post-link optimizer for the PowerPC architecture. It consists of an instrumentation engine, which processes object code, runtime library, and a GUI. I wrote the entire product, from scratch, by myself, in less than a year. The usage model, is that you instrument a program to collect performance data, then use that data do feedback directed code optimization. The GUI can display execution profile histogram data, program callgraph with coverage data, and function control flow data, with coverage data. MrCpp is a C++ compiler for the PowerPC architecture. I designed and implemented two major enhancements to MrCpp. First, I added a new datatype, 64 bit long, with multi-instruction sequences generated for operations, since the target machine was 32 bit. Later, I added support for the C++ exception model that had recently been added to the C++ standard.

Worked on PA8000, IA64, and Pascal Compiler products. PA8000 was the first 64 bit PA-RISC chip. During its design, I wrote a performance simulator/emulator for the chip, and ran spec92 benchmarks on the simulator. It was a cycle accurate performance simulator that ran object code programs, modeled the out-of-order pipeline and generated correct program execution results. It was used for design tradeoff analysis by the hardware team, and was used by the compiler team to tune the compiler. Its GUI had debugger functionality, and also visualization of the pipeline internals. I was also a member of the PA-RISC architecture committee. IA64 was originally an HP labs project, which was later shared with Intel. Before Intel was called in, I was part of a team that was charged with doing a performance analysis of the new architecture. My part of the analysis was to analyze TPC benchmark performance.I accomplished this by writing an object code translator, that given PA-RISC object code, and an execution trace from a PA-RISC system running that code, my tool generated a new execution trace, with IA64 instructions, that was then fed into an IA64 trace driven simulator. I worked on a project that retargeted the Apollo Domain Pascal compiler from DN10000 to PA-RISC, and ported it to HP-UX.

Worked on MC5700, VA1, and TMM products.The MC5700 is an 8 processor SMP system, using MC68020 processors. It ran a Realtime UNIX, derived from BSD. My responsibility was to add multiprocessing support to the kernel. The VA1 is an array processor board for that system, built with bitslice technology. My responsibility was the kernel driver, the microcode loader, and the virtual DMA microcode. The TMM, is a second generation memory controller for that system. It featured pipelined operation, to go with the pended bus protocol that supported the SMP system. I designed the board using 74F series TTL logic, PALs, and 1MBit DRAMs.

Worked on 68K Workstation and 68K SBC products. I ported UNIX to a 68K-based workstation. I also designed a 68K-based single board computer.

Worked on UNIX/1100, and PWB RJE products. UNIX/1100 was a port of UNIX to a UniSys 1100 mainframe. It was the first SMP UNIX implementation, and the fourth UNIX port ever. At first, I worked on the kernel, and then later I worked on the C compiler. I also wrote the assembler.PWB RJE was part of the Programmer's Workbench project. Here, UNIX was used to front end a mainframe, emulating a remote job entry station, and providing a friendlier development environment for the application programmers. My responsibility was to maintain it, and port it from the PDP-11 to the VAX-11/780.