Eric Padilla Email & Phone Number

Santa Clara, California, Us

Develop and execute strategies to improve tool uptime and reliability across Dry Etch toolsets in Intel Fab 42. Role is a mixture of managing large projects and driving results through others as well as serving as a technical resource to execute difficult tasks and up-skill teammates.Responsible for advising/leading multiple teams to accomplish a variety of tasks relating to manufacturing, including development of dept-wide scripts for data analysis/reporting, leading forensic analysis of maintenance events to identify improvement opportunities, leading structured tool-down problem solving efforts, developing Engineer/Technician training and relationship-building programs, and driving procedure/documentation matching and improvement.

Santa Clara, California, Us

Sustain and direct maintenance on multiple VLSI Dry Etch systems in Intel Fab 32. Duties include process control, parts and repair management, test wafer management. Specializing in automated data analysis and reporting to eliminate manual engineering work. Responsible for managing relationships with maintenance technicians, equipment suppliers, sister factories, and other F32 toolsets as well as responsible for reporting out on equipment performance to factory-level teams and staff.

Santa Clara, California, Us

Process engineering rotations in Thin Film deposition and Dry Etch areas, as well as a rotation as a Data Visualization Engineer working on automated reports used by Factory staff and Factory wide.

Tempe, Az, Us

Worked under an SRC/EA Masters Scholarship for Prof. Nik Chawla. Research topics focused on X-ray microtomography studies of Pb-free SAC solder alloys and x-ray imaging their mechanical deformation in 3D.

Los Angeles, Ca, Us

Prof. Mark S. Goorsky Lab - Electronic Materials Group:Strain Modeling of Hydrogen Ion-Implanted Semiconductors Using High Resolution X-ray Diffraction (Intel Scholar – CEED RISE-UP Program)• Modeled strain profiles to fit XRD data of H+ implanted GaN, Si, InP using Bede RADS• Determined how annealing temperature and duration affected strain evolution in GaN• Corroborated results with TEM images, and characterized implanted microstructureIntegration of Si and InP using Wafer Bonding and Layer Exfoliation • Etched and characterized Si surfaces using IR and AFM to determine waferbonding suitability• Patterned Si wafers using photolithography, and wafer-bonded using PECVD SiN bonding layer and RIE oxygen activation for use in Ion-Cut process.

Ms, Materials Science And Engineering

Bs, Materials Engineering