Eric Upson Email & Phone Number

Portland, Oregon

Coming soon.....

Dupont, Wa

Software architect and senior software developer on the Intel ITP (In-target probe) JTAG run-time debuggerThe ITP product creates human-usable abstractions of complex silicon debug interfaces to validate and debug every piece of silicon manufactured by Intel. ITP is comprised of a large software stack plus a USB/PCIe FPGA hardware probe that plugs into a target silicon device under test. Like Visual Studio, it can be used to break execution and step through BIOS, firmware, kernel, and device driver software running on a live system. It traces real-time instruction execution, interrupt handling, power state transitions, and IO bus traffic for PCIe, QPI and memory. ITP is used by many validation groups within Intel and by large OEM customers outside of Intel such as Apple, DELL, and HP.Technology: C# .Net, Mono Linux, XML, Python, C/C++, multi-threading, SOA architecture, Unity Framework, .Net remoting, IPC, USB, PCIe, WDF driver, JTAG, I2C, FPGA, and firmware. Developed using scrum with cross-site and multi-GEO development teams.Development tools include Perforce, Subversion, Visual Studio, CodeCollaborator and TeamCity. Fully integrated build, test and deployment automation. Significant regression infrastructure running 80+ live and virtual system configurations.Required skills include strong computer architecture background, low level instruction set knowledge, OO design, hardware/software integration and full stack debug.

Dallas, Texas

Performed IC schematic entry of several microcontrollers using Cadence Opus and ModelSim. Verified captured schematics by SVS and LVS comparisons using Cadence Dracula. Resolved numerous MOS length and device discrepancies produced through schematic verification.