Eric Stubblefield Email & Phone Number

Santa Clara, California, Us

San Jose, Ca, Us

Low-power IoT ASIC – “from scratch” SoC VerificationTestbench written in System Verilog / UVM.• Led team of 6 DV engineers in India in SoC verification of peripheral and timer blocks: reviewed verification plans, oversaw schedule estimates & regressions and mentored junior engineers on technical and tools problems.• Wrote verification plan for SDIO, instantiated VIP in testbench, helped new DV engineers up to speed in writing first tests.• Wrote SoC verification plan, made schedule estimates.• Wrote Digital Always-on clk, reset & power mode control block verification plan and helped new DV engineer up to speed.• Researched & wrote register access test of ~1k RF/analog bits and debugged initial Gate Level Sim (GLS) testcase for test chip tape-out.

Timpanogas wearable medical biometrics chip controller -- SoC Verification• Wrote new System Verilog / UVM testbench for SoC-level integration for DUT containing ARM M55 & M0+ controllers, an ARM NIC and various 3rd party IP’s• Enabled ARM controllers to be optionally replaced by UVM AHB Master Agents in SoC testbench• Added testbench features to support “C” running on ARM controllers to print arbitrary messages to UVM sim.log file, to end the testcase as pass or fail and to run hybrid “C”/UVM testcases• Wrote constrained-random UVM testcases; wrote “C” code using Keil ARM compiler, loaded hex files into DUT ROM and ITCM and had ARM controllers executed the “C” code in RTL simulations• Enhanced Mentor Register Assistant tool flow to generate hierarchical SoC-level RAL block, RTL and html files, then incorporated RAL block into testbench to be accessed by either AHB Master Agent

San Jose, Ca, Us

SoC-level and block-level verification on multiple WD enterprise NAND-flash SSD Controllers.Led cross-site, cross-organizational team to integrate new encryption block into SoC. Scoped verification effort of several blocks from specs and interaction with RTL designers and architects, wrote and maintained verification specs and verification plans and was responsible for meeting schedules. Created, debugged & maintained clean-sheet and leveraged System Verilog UVM testbenches, wrote testcases and debugged regression failures, closed functional and code coverage. Verified integration of external company's IP into ASIC and worked with Taiwan- and India-based engineers, contractors and external vendors.Western Digital verification engineer embedded in HP-Enterprise's ASIC ReRAM Controller design team.Scoped tests of ReRAM-interfacing block, made schedule estimates, added environment features, wrote verification IP and sequences and debugged and fixed test failures. As point of contact for SanDisk BFM releases to customer, set up SFTP drop box and JIRA bug database, communicated customer feedback to resolve major release faults. Interviewed and on-boarded verification engineers.

Assured functional correctness of RTL design through modern verification techniques. Created verification and test plans based on design specs and reviewed with RTL designers. Architected, designed and debugged UVM verification environment, including class-based test bench and components. Wrote environment and post-processing scripts as needed.

Fremont, Ca, Us

Verified IP blocks for several Enterprise & Client SSD Controller ASIC designs, meeting or exceeding milestone requirements. Gathered requirements for, architected, implemented and debugged multiple verification environments and their components in UVM or VMM with System Verilog. Created and maintained verification plans, test plans and schedules. Interfaced with other groups delivering block IP and with system integration for methodology and delivery requirements. Wrote constrained random and directed test cases and analyzed and closed coverage.Selected accomplishments:• Led read datapath verification, delivering high quality RTL and verification IP (VIP) with system integration team integrated into chip-level environment.• Coordinated milestone releases to cross-site system integration team and periodically updated block IP environment with new vendor library cell releases, successfully releasing block IP to system integration at multiple milestones.• Wrote and maintained variety of UVM & VMM components, including constrained-random stimulus (sequences), scoreboards, data classes, transactors.

Verified IP blocks for SAS Expander chip, working with on-site and cross-site RTL designers and verification engineers. Maintained and debugged random verification environment for Virtual Port Engine (VPE) and triaged and debugged tests for VPE and Expander Port Engine (EPE).• Maintained and debugged System-C/C++ VPE meta-checker and random stimulus and VPE & EPE constrained-random test cases.• Verified SGPIO functionality with I2C meta-checker and random test cases.

Houston, Texas, Us

As member of system integration team, verified that assembled block IP functioned correctly at chip level, ultimately yielding high quality first silicon. Wrote and maintained test bench components and constrained random stimulus for SoC's verification environment. Wrote, triaged and debugged random and directed system-level tests. As member of cache characterization team, led software development team in porting C++ based cache BIST compiler and writing cache tests for first silicon characterization and production.• Wrote and maintained System-C/C++ transactors, protocol checkers, monitors, constrained-random stimulus and delay element.• Wrote, triaged and debugged constrained random and directed system integration test cases, completing coverage closure.

Houston, Texas, Us

Block Verification, PA-8900 CPU (1/2001 – 10/2001)Software Engineering, PA-8700 CPU (4/2000 – 12/2000)Block Verification, PA-8700 CPU (2/1999 – 3/2000)Setup Production Test / Value Chain / Tools Writing PA-8500 CPU (4/1996 – 1/1999)Physical Design, PA-7300LC & U-Shrink CPU (4/1994 – 4/1996)

Masters, Electrical Engineering

Bachelors, Electrical Engineering