Responsible for functional verification of PPU (Parallel Processing Unit), integrating Synopsys EV7x ARC Core and using MetaWare toolchain (HW/SW verification). From specification to signoff, requirement based verification functional and structural coverage based signoff, including Certitude testbench qualification. Useful experience of 3rd party IP integration verification, remotely coordinating work with international team and split of responsibilities (including software and safety topics). Major contribution in enabling Synopsys to release their first ASIL-C STL (Software Test Library) for EV7x cores. First silicon out and running fine.Part of the team defining and implementing the ASILB safety case for Infineon TriCore SBST (Software Based Self-Test). Responsible for tool qualification and technical documentation according to ISO26262 requirements.Working on next generation SBST for CPU and SPU (Signal Processing Unit).Technical contributor for EMC2 European project (WP6 - System qualification and certification).Aurix 2nd and 3rd Generation functional verification.

Back to a mainly technical role as Principal Engineer for the Automotive Micro Controller group looking after the development of TriCore SBST (SW Based Self Test). Task force leader and part of the expert team defining and coordinating the safety qualification of Infineon AURIX TriCore MCU.Technical contributor for VeTeSS (Verification and Testing to support functional Safety Standards) European project (WP5 - Simulation and modelling).

Responsible for the coordination of a 17 people verification team and for the quality of all of Bristol IP.Technical coordination of TriCore verification. Major contribution in releasing several first time right complex MCU.IP Verification Technical leader for Infineon AIM MC D division.

Responsible for the quality of the TriCore 32 bit microprocessor family, cores aimed at the embedded market, including safety critical applications.Under my management state-of-the-art verification methodologies, such as directed and coverage-driven random testing, assertions and formal methods, have been successfully integrated in the verification flow.Two TriCore derivatives completely re-verified using the new flow achieved high quality criteria. The new generation TriCore2 verified with the new flow is now in silicon and no bugs have been found.Coordinating and actively verifying the second generation TriCore2 (higher performance and improved functionalities).

Team leader of TriCore2 (TC2) Verification for Infineon AI-MC.TriCore2 is the second generation Multithreaded core of the TriCore architecture, the 32 bit Infineon Microcontroller.Experience in team management (5 people) and work planning, work co-ordination with design team and verification team split across two sites. Definition of CPU verification flow, sign-off criteria, random testing strategy, development of test specification, co-ordination and work on Specman Instruction Stream Generator (ISG) and test generation.Since 09/2002 Major team reorganisation due to Infineon consolidation of all TriCore activities in Bristol design centre, resulting in increased responsibilities and span of control. Only responsible for TC2 verification.Planning and co-ordination of knowledge transfer activity for TriCore verification; Task successfully completed on aggressive schedules.Management of a 10 people team through TC2 project successful completion. Test Specification and flow definition/implementation for the Multi-Threading release of TriCore2. Definition of a run time configuration mechanism to maximise reuse of existing directed test suite (increased randomness) and to reuse existing single threaded tests to verify multithreading. Introduction of formal methods and functional coverage in the flow.

Spent the first three months in San Jose (CA) to migrate to Bristol the TriCore verification environment (Multi Site project). Set-up of the environment in Bristol and start to work on the verification of TriCore.Experience in Memory system test specification and implementation.Leading of a small team (3 people).

Functional verification consultant for STMicroelectronics MCDD (Micro Cores Development Division, group split between Bristol and Catania).Experience in block, CPU and System level verification of SoC products, system and CPU assembly tests development, checking mechanism implementation, formal verification and code coverage.Development of an innovative verification flow used for the C2P (stack architecture), the 100Mhz/32bit microcontroller used in MCDD embedded system products.Developed scripts to automate the flow, integrated for the first time TransEDA VHDLCover coverage tool and Formality equivalence checker.