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Fen Chen Email & Phone Number
Principal PDE and RAS SME for GenAI Products
at
NVIDIA
1 work email found
@getcruise.com
4 phones found area 802 and 408
LinkedIn matched
4 data sources
Profile completeness 100%
Current company
Role
Principal PDE and RAS SME for GenAI Products
Location
Morgan Hill, California, United States
Company size
Who is Fen Chen? Overview
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Quick answer
Fen Chen is listed as Principal PDE and RAS SME for GenAI Products at NVIDIA, a company with 41500 employees, based in Morgan Hill, California, United States. AeroLeads shows a work email signal at getcruise.com, phone signal with area code 802, 408, and a matched LinkedIn profile for Fen Chen.
Fen Chen previously worked as Principal PDE/RAS SME for GenAI Products at Nvidia and Principal Product Integrity Engineer, Manager at Cruise. Fen Chen holds Ph.D., Electrical Engineering from University Of Delaware.
Company email context
Email format at NVIDIA
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{first}.{last}@getcruise.com
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AeroLeads found 1 current-domain work email signal for Fen Chen. Compare company email patterns before reaching out.
Profile bio
About Fen Chen
With over 60 published papers, invited talks, and two book chapters, I have a specialized focus in semiconductor reliability. My work has led to the issuance of more than 60 U.S. and international patents. My areas of expertise encompass semiconductor reliability and quality, consumer and automotive product reliability, microelectronic device fabrication and processes, as well as device and circuit electrical characterization and testing (both DC and RF). I am also an experienced reviewer for leading industry journals, including Applied Physics Letters, Journal of Applied Physics, IEEE Electron Device Letters, IEEE Transactions on Electron Devices, Microelectronics Reliability, Journal of Vacuum Science & Technology, and Journal of the Electrochemical Society. I have chaired the JEDEC JC-14.2 subcommittee for 5 years and led the IRPS BEOL dielectric technical committee for 4 years.
Listed skills include Semiconductors, Reliability, Failure Analysis, Testing, and 46 others.
Current workplace
Fen Chen's current company
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Nvidia
8 roles
Fen Chen work experience
A career timeline built from the work history available for this profile.
Principal Pde/Ras Sme For Genai Products
Current
Nov 2024 - Present
Principal Product Integrity Engineer, Manager
- Lead a team to develop and conduct reliability qualifications based on Cruise AV-specific mission profiles to ensure that Cruise groundbreaking AV hardware systems with electronic, optical, and electromechanical modules meet automotive industry high-level reliability and zero-defect quality specifications.- Collaborate with global suppliers to execute.
Jul 2019 - Oct 2024
Director Of Quality And Reliability
- Led qualification of novel LED product with knowledge-based Reliability testing at chip, package and L2 board levels for automotive applications- Utilized Six Sigma/SPC/QSM methodologies to identify and resolve design and manufacturing challenges, driving continuous quality improvement.- Participated in activities of AEC Q102 revision, BLR, and MCM.
Feb 2019 - Jul 2019
Senior Reliability Engineer
Responsible for the reliability of novel Apple products, materials, and supplier technology. - Performed FMEA and identified high-risk failure modes early in the design life cycle.- Conducted critical risk assessments for various failure mechanisms with new reliability model and methodology developments.- Guided and empowered suppliers to conduct.
Jun 2015 - Feb 2019
Senior Reliability Engineer
Worked on various semiconductor technology reliability mechanisms including low-k TDDB, high-k TDDB, metal electromigration, metal stress voiding, MOL PC-CA spacer dielectric TDDB, etc. Developed industry first low-k TDDB model (square-root of E acceleration model) in 2006 and testing methodology (author of JEDEC JEP159) in 2009.Pioneered semiconductor MOL.
Jun 1998 - May 2015
Graduate Intern
Worked at Intel Component Research on EM and SIV related failures for interconnects. Developed new Al layered structure for better reliability applications. Discovered and proposed the industry first Cu resistivity size effect in 1998.
Aug 1997 - Mar 1998
Graduate Co-Op
Tested stress and recovered error for IBM AS/400 system. Verified redundancy, proper failing behavior and proper recovery. Proceeded with SPD Bus error injection, optical cable error injection, and user interaction testing.
Jun 1997 - Aug 1997
Team & coworkers
Colleagues at NVIDIA
Other employees you can reach at nvidia.com. View company contacts for 41500 employees →
RR
River Riddle
Colleague at Nvidia
Fort Collins, Colorado, United States, United States
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PG
Parush Garg
Colleague at Nvidia
San Francisco Bay Area, United States, United States
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RP
Ramakrishna Prabhu
Colleague at Nvidia
Austin, Texas, United States, United States
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GO
Gustavo Ovalles
Colleague at Nvidia
United States, United States
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NC
Noam Cooper
Colleague at Nvidia
Herzliya, Tel Aviv District, Israel, Israel
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DA
Dimitri Ababii
Colleague at Nvidia
Paris, Île-de-France, France, France
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IK
Ingrid Kelly
Colleague at Nvidia
San Francisco Bay Area, United States, United States
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MC
Matias Codesal
Colleague at Nvidia
Raleigh-Durham-Chapel Hill Area, United States, United States
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UJ
Uttara Joshi
Colleague at Nvidia
Pune, Maharashtra, India, India
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MS
Mark Stephenson
Colleague at Nvidia
Austin, Texas, United States, United States
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River Riddle
Colleague at Nvidia
Fort Collins, Colorado, United States, United States
View →
PG
Parush Garg
Colleague at Nvidia
San Francisco Bay Area, United States, United States
View →
RP
Ramakrishna Prabhu
Colleague at Nvidia
Austin, Texas, United States, United States
View →
GO
Gustavo Ovalles
Colleague at Nvidia
United States, United States
View →
NC
Noam Cooper
Colleague at Nvidia
Herzliya, Tel Aviv District, Israel, Israel
View →
DA
Dimitri Ababii
Colleague at Nvidia
Paris, Île-de-France, France, France
View →
IK
Ingrid Kelly
Colleague at Nvidia
San Francisco Bay Area, United States, United States
View →
MC
Matias Codesal
Colleague at Nvidia
Raleigh-Durham-Chapel Hill Area, United States, United States
View →
UJ
Uttara Joshi
Colleague at Nvidia
Pune, Maharashtra, India, India
View →
MS
Mark Stephenson
Colleague at Nvidia
Austin, Texas, United States, United States
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1 education record
Fen Chen education
-
University Of Delaware
FAQ
Frequently asked questions about Fen Chen
Quick answers generated from the profile data available on this page.
What company does Fen Chen work for?
Fen Chen works for NVIDIA.
What is Fen Chen's role at NVIDIA?
Fen Chen is listed as Principal PDE and RAS SME for GenAI Products at NVIDIA.
What is Fen Chen's email address?
AeroLeads has found 1 work email signal at @getcruise.com for Fen Chen at NVIDIA.
What is Fen Chen's phone number?
AeroLeads has found 4 phone signal(s) with area code 802, 408 for Fen Chen at NVIDIA.
Where is Fen Chen based?
Fen Chen is based in Morgan Hill, California, United States while working with NVIDIA.
What companies has Fen Chen worked for?
Fen Chen has worked for Nvidia, Cruise, Lumileds, Apple, and Ibm Microelectronics Division.
Who are Fen Chen's colleagues at NVIDIA?
Fen Chen's colleagues at NVIDIA include River Riddle, Parush Garg, Ramakrishna Prabhu, Gustavo Ovalles, and Noam Cooper.
How can I contact Fen Chen?
You can use AeroLeads to view verified contact signals for Fen Chen at NVIDIA, including work email, phone, and LinkedIn data when available.
What schools did Fen Chen attend?
Fen Chen holds Ph.D., Electrical Engineering from University Of Delaware.
What skills is Fen Chen known for?
Fen Chen is listed with skills including Semiconductors, Reliability, Failure Analysis, Testing, Cmos, Design Of Experiments, Ic, and Electronics.
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