Maththaiya Durai Email & Phone Number

My Skills and Experience are as follows -- Hands on Experience in RTL design using Verilog and System Verilog - Hands on Experience in ASIC verification using System Verilog- Good Knowledge of ASIC and FPGA design and verification flow- Skilled in RTL coding, proficient at synthesis and verification using System Verilog- Good Knowledge of PERL,PYTHON coding and task automation using PERL and PYTHON- Proficient in timing analysis in digital systems, creating and implementing state machinesTechnical Skills:-- Hardware Description Language : Verilog, System Verilog.- Verification Methodology : UVM, OVM (basics).- Hardware Tools : Synopsys VCS, Synopsys Design Compiler, Xilinx ISE, Matlab, ModelSim, Simulink, PSpice, LEdit, Keil, Spartan3E, Cadence.- Scripting Language : PERL, Python ,Tcl.- Programming Languages : C, C++, Matlab, PL/SQL, Oracle, x86 Assembly Language 8085/8086 .- Operating Systems : Windows, Linux (Red-Hat & Ubuntu).- Specialties : RTL Design, ASIC Verification, Computer Architecture, FPGA, Emulation, Validation, Characterization , Testing

Listed skills include Embedded Software, Graphics Design, Computer Architecture, Linux, and 33 others.