Jonathan Young Email & Phone Number

Newburyport, MA, US

Natick, MA, US

FPGA development for Signal Processing and Communications Projects included work on topics including MIMO, RADAR jammers/anti jammers, Navigation, Nuclear Power Control and Electric Vehicle Motor Control. Worked with QR decomposition, PolyPhase Channelizers, Resample filters, Mixers, FIR filters, FFT/IFFT and Matrix inversion in both fixed point and.

Design, code, simulate, test and debug FPGAs. Telecom with speeds up to 100G. DSP projects from sonar to RF. Xilinx, Lattice, Altera parts to the latest available. Worked with matlab and simulink tools for designs.

New York, NY, US

Designed FPGAs for SONAR systems including NCO, I/Q mixer, decimating FIR filter, matched complex filters and chirp signal generation. Met a four-month schedule in two weeks.

San Jose, California, US

Design, simulate debug FPGA used in the 100Ge tester.

Somerville, Massachusetts, US

PCIe, DDR3 memory interface, DSP components such as DDS, filters, mixers. components for quantum computers. GPS interface. Virtex 6 and 7 devices. Xilinx ISE, Vivado and system generator. modelsim/questasim. UART, SPI, USB, I2C, GPIO.

Developed adaptive filter to help suppress unwanted signals in RF communications

Digital signal processing including complex floating point numbers for add/subtract/multiply/divide/square root, filters: FIR/IIR/adaptive/Hilbert/CIC, trig functions, mixers, oscillators: LO/DDS/NCO, modulation/demodulation. Matlab to RTL conversions. Test benches and simulations and lab debug.

US

Designed FPGAs for 43Gb/s long haul telecom. SONET/OTN/10GE. Evaluation platform: FPGA ran at 330 MHz to generate and verify 43 Gb/s PRBS data in SFI5 format (2.7Gb/s). 4x10 platform combined 4 - 10GE streams into one 40Gb/s link. PMDC100 - DSP functions such as filters, log, divide, and square root. MI5000XM, MI4000XM and LIC – bias loop dither.

Provided Gigabit Ethernet access to NASDAQ. Processed stock trades in hardware based on proprietary algorithms that were tunable on the fly. Embedded processing was used as well for overhead functions. Designed embedded processor and hardware based internet protocol for hardware based stock trading. Used Xilinx Embedded Development Kit (EDK) Virtex 5 330.

Somerville, Massachusetts, US

Navajo: Designed FPGAs for Quantum Cryptography system. Functions include: key sifting, privacy amplification, pseudo random bit stream generation, data collection, and control of the lasers and optics with clock speeds of 310 MHz. All designs were completed ahead of a very aggressive schedule.

St Petersburg, FL, US

40G SONET/OTN FPGA design work.

Beaverton, OR, US

OTS9100: Specified, designed, implemented and debugged Receiver FPGAs for OC768/OC192 SONET/SDH 10Gb/s testers using Xilinx parts up to Virtex II 6000. Functions included: PRBS payload verification, overhead verification, alarm and defect monitoring and forward error correction.

Chelmsford, MA, US

Merlin: SKYbolt2 Arithmetic Platform: G4 PowerPCs 500MHz core, 1.0 GByte 83.3 MHz SDRAM, SKYchannel interface in a 6" x 6" space. Lead the overall architecture development. Divided the functionality into separate parts to best suit the performance, and the design team, trading off cost, real estate, signal integrity, performance, power, design time, and.

US

IM-VME: Three 2MByte frame memories. Each quad ported with total bandwidth of 200 MBytes/Sec. True color video acquisition and display in a 6U VME form factor. Designed, implemented, debugged and released in to production. Supported customers.

Designed and implemented the instruction decoder for their 80486.Applications engineer for video compression chip.

US

Design debug and support machine vision projects. Video board design. FPGA design using Xilinx, Lattice, Actel and Quicklogic.

Boston, MA, US

Let a group of 12 engineers in designing projects for C3I.

Design of hardware for C3I

Atlanta, Georgia, US

Product engineer for the first 32 bit CPU. Yields, reliability, functionality.

Msee, Digital Signal Processing

Bsee, Digital Design