CPU Formal Verification:- Verification of clock gating in L1 memory subsystem.- Development of multi-unit overconstraints to support end-to-end checks.- Modeling of design reductions and mutations to increase proof's depth.Engineering rotation (4 months): Security Verification.- Formal Verification (Jasper SPV) to verify unauthorized access to external system registers.Engineering rotation (4 months): FuSa Verification.- Automation of fault trees creation and… Show more CPU Formal Verification:- Verification of clock gating in L1 memory subsystem.- Development of multi-unit overconstraints to support end-to-end checks.- Modeling of design reductions and mutations to increase proof's depth.Engineering rotation (4 months): Security Verification.- Formal Verification (Jasper SPV) to verify unauthorized access to external system registers.Engineering rotation (4 months): FuSa Verification.- Automation of fault trees creation and analysis using EDA tools and scripting plugins. Show less

Validation of Software Test Libraries (STLs):- Development of UVM checkers and coverpoints. - Creation of python scripts to parse and analyze assembly code, targeting code coverage.- Prototype for a .tcl code debugger (parsing tarmac/disassembly) as plugin for QuestaSim.