Frank D. Email & Phone Number

Usa

Extensive travel and play.

Broomfield, Co

ASIC Design: Developed architecture and coded, using synthesizable Verilog, an eighty thousand gate queue manager, incorporating Quality of Service (QoS), hardware trunking, and Arbitrated Loop algorithms into a state machine used to search a linked list structure. Proved design concepts via lab emulation, where reduced clock rate caused FPGA prototype specific clock boundary crossings.ASIC Verification: Developed comprehensive suites of tests for specified design blocks using code coverage, revision control, SDF annotation, and gate level simulations. Wrote Verilog model to emulate system level functions for use in verifying specified design blocks. Implemented system of robust, user friendly PERL scripts that allowed the design community and the verification engineers to share a common set of commands for running individual tests as well as full regressions. Developed working knowledge of Vera object oriented test language. Developed working knowledge of Fibre Channel and Arbitrated Loop protocols.

Fort Collins, Co

Software Verification: Conceived, designed, implemented in PERL, and tested a strategy for regression testing of software projects.

Louisville, Co

Hardware Verification: Developed Mentor QuickSim board level simulations. Developed hardware model for use with Mentor design system.

Fort Collins, Co

ASIC Library Development: Modeled SYM9 library for use with IKOS hardware accelerator. Developed IKOS Voyager and Cadence Leapfrog Model Certification Test (MCT) flows. Verified as golden the Leapfrog MCTs using golden Verilog models.

Boulder, Co

ASIC Verification: Developed Verilog simulations that tested the chip under development to given specifications. Experience with PCI and SSA protocols. Experience with Cadence Verilog and Simucad Silos.

Louisville, Co

Hardware Verification: Developed program-critical-path Verilog system simulations that initiated data transfers within the Iceberg Penguin Control Unit, thus testing the board under development to given system specifications. Converted the Verilog data transfers for use with lab emulators during hardware integration phase of board development. Maintained the Iceberg Verilog design files using UNIX revision control. Exceptional talent for using script languages to perform the repetitive tasks associated with design verification, simulation, and hardware integration.

Melbourne, Fl

Member of the Engineering Productivity Group: Ran benchmarks on available CAE tools to collect data used in the selection of a “recommended tool set.” Responsible for marketing, selling, and applications support of the recommended tools to all Harris divisions, resulting in highly developed customer and vendor interface skills.Areas of expertise:ASIC Test Pattern Services: Used ViewLogic product ViewTest (Sunrise Test Systems engine) to perform design testability analysis, scan path insertion, automatic test-vector generation (ATG), fault simulation, JTAG (IEEE 1149.1) support, and tester specific vector formatting for Harris Divisions. Experience with other ATG tools.Digital Logic Simulation: Instrumental in establishing board level simulation at Harris Information Systems Division (HISD). Served as simulation leader on several board development projects within several divisions.Modeling: Experience with modeling at the gate, hardware, and behavioral levels. Experience with software and hardware models from Logic Modeling Corporation (now Synopsys).Coding: Verilog, VHDL, C programming, and the UNIX operating system.Programmable devices: Organized trade show on programmable logic devices involving 17 vendors, 8 user presentations, and 85 Harris engineers.Training: Developed and taught a Design for Testability (DFT) course for use within Harris divisions. Developed and taught a Digital Simulation course (ViewLogic Schematic entry, CADAT logic simulation, LMC software models). Developed outline for a VHDL course with emphasis on logic synthesis.

Palm Bay, Fl

Design Automation: Worked with the Daisy CAE system. Held secret clearance. Designed, wrote, tested, and documented a schematic-tree netlist comparison software program (Daisy proprietary language). Modified an existing applications program to include the designer’s notes with the netlist information being routed to the layout department. Determined the relationship between the abstract output of the Daisy Testability Analyzer (DTA) and the concrete output of the Daisy Fault Simulator (DFS).

Palm Bay, Fl

Digital design: Held secret clearance. Experience with state machines, on-line self testing, and off-line self testing. Designed, breadboarded, debugged, and documented TTL board designs.

Manassas, Va

System availability management: Held secret clearance. Experience with fault mapping, baseline fault insertion, and Built-in Test Engineering (BITE) techniques. Experience interfacing with U.S. Government and external companies.

Salem, Va

Developed a software alarm and display package (FORTRAN) for an automated steel mill using a DEC PDP 11/70 computer. Worked with high voltage (30,000 volts) and high current (140,000 amps) on an electrostatic precipitator project. Hands-on experience with transformer design, construction, and use. Hands-on experience with laboratory equipment. Designed, constructed, and tested TTL digital circuits.