Fred Wu Email & Phone Number

Metuchen, Nj

Responsible for data preparation with Alteryx and Tableau Dashboards-Interact with clients to formulate business requirements.-Deliver proof of concept (POC) to visualize sample data.-Identify KPIs based on the client’s dataset.-Design and Modify data sets to meet their requirements.-Build and Implement Tableau Dashboards.

San Diego, Ca

I supported and the characterization of memory and fuse PROM test chips in TSMC, 28nm low power and 28nm metal gate processes. This involved working with designers to determine and prioritize parameters for characteriztion, creating test programs on the Verigy Smarttest platform for data collection, and analyzing and presenting the data to designers. If silicon data did not match simulation data, I worked with designers to debug. When data was approved by designers, I would publish internal documation of the results.

San Diego, Ca

I supported and lead the characterization of digital blocks (I/O pads, memory, processors, digital interfaces) of various MSM (modem) chips in TSMC and IBM, 65nm and 45nm fabrication processes. This involved working with designers to determine and prioritize parameters for characteriztion, creating test programs on the Verigy Smarttest platform for data collection, and analyzing and presenting the data to designers. If silicon data did not match simulation data, I worked with designers to debug. When data was approved by designers, I would publish internal documation of the results. When leading characterization projects, I would keep engineers on schedule and support their efforts by providing necessary resources such as tester time and push for test vectors.

San Diego, Ca

I helped the primary Engineer with the design and verification of a fuse based read only memory bitcell and block. At the block level, using hspice and hsim, across all process, temperature, and voltage corners, I verified sensing, programming, and scan chain functionaliy. I generated timing information such as setup and hold time, clock to q delay, and clock insertion delay. In the bitcell, I helped debug the logic in the controller, and sized transistors for sense inverter and programming transitor. For integration into chips, I extracted netlists and provided test vectors. Finally, I created perl scripts for running simulations, data collection and analysis, and presentation and documentation

Masters Of Engineering, Electrical Engineering - Electronic Circuits And Systems

Bachelor Of Science In Engineering, Bachelor Of Science In Economics, Systems Engineering, Operations And Information Management, Management

Activities and Societies: Jerome Fisher Program for Management and Technology, Ben Franklin Scholar, Joseph Wharton Scholar