● Semiconductor processing technology; process integration, fabless manufacturing, thin films.● Technical & commercial reviewer of Small Business Innovation Research proposals for National Science Foundation (SBIR/STTR) – semiconductors, advanced memory devices, MRAM & IC’s, photovoltaics, batteries, MEMS, optical & electronic materials, bio-med nanotech, new manufacturing technologies, nano-instrumentation.(100 proposal reviews delivered)● Chair emeritus - IEEE Santa Clara Valley… Show more ● Semiconductor processing technology; process integration, fabless manufacturing, thin films.● Technical & commercial reviewer of Small Business Innovation Research proposals for National Science Foundation (SBIR/STTR) – semiconductors, advanced memory devices, MRAM & IC’s, photovoltaics, batteries, MEMS, optical & electronic materials, bio-med nanotech, new manufacturing technologies, nano-instrumentation.(100 proposal reviews delivered)● Chair emeritus - IEEE Santa Clara Valley Section (>11,000 members, >40 chapters & groups);Chair - IEEE San Francisco Bay Area Nanotechnology Council; IEEE-SEMI Collaboration - Core Team; FSA/GSA IP Licensing Risk Assessment Tool Working Group & Model License Agreement Review Committee member. Show less

Educating and Inspiring fledgling engineers

Mission: Troubleshoot and turn-around all aspects of a compound semiconductor (wafer fab) factory's operations. Reporting department managers: Engineering, Production, Maintenance, Facilities.● Increased yields 100%, reduced manufacturing cycle times 50%, increased wafer output 200%, increased productivity 500%.● Improved engineering, wafer fab operations, product delivery schedules. Eliminated late deliveries.● At close of 2 year tenure: managed product build-outs, fab closure… Show more Mission: Troubleshoot and turn-around all aspects of a compound semiconductor (wafer fab) factory's operations. Reporting department managers: Engineering, Production, Maintenance, Facilities.● Increased yields 100%, reduced manufacturing cycle times 50%, increased wafer output 200%, increased productivity 500%.● Improved engineering, wafer fab operations, product delivery schedules. Eliminated late deliveries.● At close of 2 year tenure: managed product build-outs, fab closure, and manufacturing transfer to new factory located in the United Kingdom. Show less

● Implemented $20 million, first high revenue turn-key production (wafer + test + package). ● Resolved customer issues and problems in design, development, prototype and production.● Sales support with technical presentations; technical consulting for quotations and contracts.● Developed wafer acceptance criteria, procedures, documentation, for customer/foundry engagements.● Managed: design acceptance, intellectual property (IP), design rules waivers, DRC, OPC; reticles; unique… Show more ● Implemented $20 million, first high revenue turn-key production (wafer + test + package). ● Resolved customer issues and problems in design, development, prototype and production.● Sales support with technical presentations; technical consulting for quotations and contracts.● Developed wafer acceptance criteria, procedures, documentation, for customer/foundry engagements.● Managed: design acceptance, intellectual property (IP), design rules waivers, DRC, OPC; reticles; unique customer process requirements, process and product qualification, reliability; testing; product acceptance criteria and standards, yield enhancement.● Start-up pure-play wafer foundry ● AWFS Patent & Technology Review Board.● Fabless Semiconductor Association (FSA => now GSA) liaison; Foundry Qualification, WLR Reliability committees member. Show less

● Resolved $1 million / month problem - as director of successful yield-bust task force. Assigned to lead all subsequent yield-bust task forces.● Yield enhancement, device, process analysis; CMOS microcontrollers w/ ROM, EPROM; bumped flip-chips.● Analyzed parametrics, yields, Six Sigma control, TQM issues. Process transfer & sustaining engineering.● Coordinated analytical services for wafer fab by in-house and outside laboratories

● Achieved 29% defect density reduction over a six month period.● Led defect reduction team of engineers and technicians. (Opt-in 5% - 10% work hours of all fab engineers, technicians, supervisors)