Gary Lang Email & Phone Number

San Francisco South Bay Area

San Jose

Teranetics was acquired by PLX Technology, and then the group was "spun out" to Entropic. The following is a description of all three:· Part of chip bring-up team for 10GBASE-T PHY in both 90 and 40 nm versions with register level debug· flip-chip BGA package design for quad port PHY; aQFN package design for dCSS chip· Design of dual FPGA validation board.

Sunnyvale, CA

PLX Technology sold the acquired assets from Teranetics to Acquantia and Entropic. See Entropic (above) for description of work.

Teranetics was acquired by PLX Technology in 2010, then the group was split and sold to two companies: Acquantia for the 10GBASE-T PHY and Entropic for the satellite TV chip.See Entropic (above) for description of work done from 2008 thru today.

· Lead engineer on PCIe MiniCard and Half-Minicard reference designs for low-cost 802.11 b/g card for direct production by contract manufacturers. This product required very precise layout, due to its low-cost implementation and reduced component count. Successfully positioned to go into production in the near future for Tier 1 laptop manufacturer.·.

Member of five person team to specify and design next generation FC to GbE product· Developed the system-level concept for 4-channel fiber-channel over Gigabit Ethernet encapsulating bridge· Worked with outside design firm for industrial, mechanical and thermal design

· As part of 7 person team, defined and designed a multi-gigabit aggregating edge router targeted for Central Office· Designed OC12c PoS uplink, redundant switch fabric, passive backplane, CT3 port card· Defined and designed redundancy requirements· Worked with ME and outside consultants to define mechanical and thermal constraints· Part of small team.

· Developed and designed the 32x32-bit full crossbar switch; HIPPI PCI NIC; Ethernet interfaces for switches; a HIPPI interface and controller for high speed D1 tape drive; fiber optic interfaces to crossbar switch products, which operates at 1.2 Gbit/sec· Principal responsibilities were design and support of HIPPI products. Technical responsibility for.

Sunnyvale, CA

· Technical lead for a high performance airborne signal processing and direction finding system.· Surface mount packaging and ARGOS - designed ASICs allowed this complex function to be contained in full ATR long chassis.· Responsible for cost/schedule planning/tracking and technical management.· Was principal presenter at major program design reviews with.