Android Smart Access Manager (SAM). Modified an Android video player to run on top of SAM that selects a WLAN or cellular connection (Java). Modified SAM to use speed as a controlling factor to control the frequency of WLAN scans. Ported HEVC decoder to Android ASUS Tablet (4 ARM cores). Used Eclipse and NDK for build environment. Used Java to launch native C++ code. HEVC. Modified HEVC encoder and decoder to support Scalable Video Compression. Video compression. Used SIMD assembly code to accelerate video up sampling algorithm on both Windows based PC and Android. Used JNI to execute the code on a Qualcomm Android phone.LTE. Evaluated and selected a vendor for LTE. Performed code reviews on delivered code and generated problem reports. Architecture is based on 9 TI DSP cores.Software Defined Radio. Analyzed and compared several SDRs. Altair, CEVA, IMEC, Sandbridge, TI TMS320TCI6488 CommAgility BoardDSP Manager 2000-2009.Manager of DSP group. 15 DSP engineers at 3 sites: King Of Prussia, Pa; Melville, NY; Montreal, Canada.Dual Mode (UMTS/GSM) ASIC. Defined L1 SW architecture. Designed, implemented and tested UMTS L1 manager and scheduler which arre responsible for interface to upper layers, control of all components, and establishing and maintaining synchronization with the base station. Includes soft handover, hard handover, measurement control, radio control and Inter RAT. ARM9 with Nucleus RTOS. Includes HSDPA and HSUPA. Initial debug was on FPGA platform, later debug on ASIC platform. Coordinated the efforts of all DSP engineers who were involved in the L1 SW.TDD (UMTS) FPGA. Defined L1 SW architecture. Implemented and tested L1 manager and scheduler. Integrated component SW. Turbo coder. MUD/SUD receiver. OSE RTOS, TI DSP. Used HW/SW co-verification in simulated environment.Ultra Phone Platform. Fixed wireless local loop. Cost reduced platform. Maintenance. Proprietary air interface.

Acoustic Simulator. Dynamic simulation of acoustic signals. Scenario control on PC. Signal simulation on DSP board.UYS-2 development. Defined requirements for the UYS-2 . Data flow graphs were used for signal processing. Microcode for signal processing primitives. Anti-Submarine Warfare Acoustic SW. Developed an approach to resolve overruns. General Maintenance. Several sonobuoy types. UYS-1 processor. Control processor with 2 arithmetic processors. Microcode for signal processing primitives. Each arithmetic processor had its own local memory. Common bulk store for longer term storage of data.IWARP evaluation. Implemented Synthetic Aperture RADAR processing on IWARP computer. 64 parallel processors with each cell connected to 4 neighbors.

RADAR Phased Array Antennae alignment. Maintenance of SW for antennae alignment.

ERAPS (sonobuoy) signal processing. Design, implementation, and test. Lead a team of 5 implementers. Signal processing primitives in microcode. Digital filtering and FFT based.Electronic Surveillance Measures for LAMPS (Navy helicopter).Tactical SW for LAMPS