Greg Huber Email & Phone Number

Johnson City, Texas, United States

Austin, Texas

Austin, Texas Area

- Managed teams in Austin, Oregon, and Malaysia that developed Intel’s Product Platform Validation (PPV) System Level Test (SLT) test collateral. Tests were used to screen all internal and external samples (prototype products), drive improvements in upstream ATE test quality, identify and drive closure of all product and platform bugs, and release factory SLT test programs that demonstrated product’s outgoing quality requirements.- Drove initiative to eliminate the SLT test in the HVM factories for SOC’s through early identification and closure of ATE test holes, driving ATE to meet customer outgoing quality requirements without the need for SLT. Applied similar methods to Client products to reduce the cost of these extremely high-volume products. This was critical to managing Intel’s cost and quality targets within the test process.- Formed and staffed new team in Austin with both experienced and recent college graduates. This team executed well, achieving new benchmarks across Intel for cost and quality.

- Recruited to drive a new vision of discipline, quality, and cost reduction on Client new product development. Identified key new positions for moderate growth. Recognized for turning team’s reputation around for being best at Intel.- The team developed and managed the outgoing quality data stream, and SLT-Measured outgoing test hole escape closure, delivering tests that met customer outgoing quality requirements with unprecedented test times.- The team delivered >$500M in cost reductions through innovations in test time reduction while maintaining or improving outgoing product quality.- Due to recognized success on Client products in Oregon, personal responsibility grew to include management of Austin, Malaysia, California, and Costa Rica teams supporting new product development in all business segments.

- Recruited to lead a department that was in danger of being “fired” by the internal customer. Turned team into the preferred solution provider, recognized by the VP and GM for establishing a close partnership, and for being aligned with the vision, cost, quality, and delivery in a very competitive business.- Managed teams in Oregon and Malaysia responsible for developing all test hardware and software for Intel’s Desktop Motherboard products.- Included both GenRad and HP/Agilent In-Circuit Test (ICT) as well as Board Functional and Outgoing Quality Monitor tests.- Worked with both internal board manufacturing and external ODMs, installing test collateral and managing performance.- Managed development of new Shmoo environmental test process that could be delivered to an ODM factory as a process quality and reliability monitor.- Drove automation at Board Functional test step, eliminating the need for operators to plug in cables and memory for both cost reduction and quality improvement.

Acted as a customer support engineer specializing in board test techniques. Worked with many of Intel's largest Client and Server microprocessor and chipset customers, assisting their board test engineering departments with strategies and software to test their board designs. Formed and managed software team that developed automatic test program generation software for Intel's chipset products, which was provided to Intel customers and test equipment suppliers.

Technical Leader in the area of board test development and software development and automation tools. Worked in various positions as a test development engineer. Used min/max simulator to model new component and board designs, and to develop test software used to validate new ASIC and board designs, and to functionally test boards in board manufacturing. Developed ICT models and board tests using Teradyne, GenRad, and HP/Agilent board testers.