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Highly accomplished Test Engineer with extensive experience in Design For Test (DFT) and Embedded Test from IC to system level. Highly effective leader and technologist with commercial (semiconductor) and military design background. Experienced with Synopsys, Cadence and Mentor Graphics test automation tools; Virage SMS memory BIST/repair. Independent, multi-tasking worker with strong reputation as mentor.Specialties: DFT Process, Core test methodologies, scan design, scan pattern compression, Automatic Test Pattern Generation (ATPG), low power DFT, Built-In Self-Test (BIST), boundary scan, memory test and repair.
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Director Of OperationsBest Robotics, IncGeorgetown, Tx, Us
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Senior Member Technical Staff, Cpu Cores DftAmd May 2019 - PresentSanta Clara, California, Us -
Senior Member Technical Staff, Dft - Semi-Custom ProductsAmd Apr 2010 - May 2019Santa Clara, California, UsDesign-for-test (DFT) methodology and implementation of AMD CPU cores.
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Director Of OperationsBest Robotics, Inc Jan 2013 - PresentDir Ops for non-profit volunteer organization re: middle school and high school robotics competition.
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DirectorCapitol Best Robotics 2001 - PresentDirector of this 501c3 nonprofit corporation with a mission to inspire and motivate middle and high-school students towards careers in engineering, science, technology and mathematics through participation in a sports-like robotics competition. President, chairman of the board and treasurer. Perform functions such as grant writing and fundraising, advertising and publicity events, partnership development, recruitment of schools, event planning and management, robotics kit procurement and distribution, field construction, volunteer recruiting, and website management.
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Member Technical Staff / Dft EngineerFreescale Semiconductor Sep 2004 - Apr 2010Austin, Texas, UsDesign-for-test (DFT) methodology, architecture and implementation for multiple complex embedded core platforms. Support multi-core SoC integration via world-wide design centers. Concentration on low-power DFT and test pattern reuse. Significant involvement in scan design, Automatic Test Pattern Generation (ATPG) and Built-In Self-Test (BIST). -
Dft EngineerFreescale Semiconductor Mar 2000 - Sep 2004Austin, Texas, Us
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Member Group Technical Staff, Dft / Test TechnologyRaytheon Systems Company 1997 - 2000Arlington, Va, UsDeveloped DFT processes and tools for Application Specific Integrated Circuit (ASIC) designs and Circuit Card Assemblies (CCA). Defined test requirements, embedded test architecture and implemented embedded test structures. Defined embedded test software (built-in test) architectures for CCA and subsystems. -
Member Group Technical Staff, Dft EngineerTexas Instruments 1985 - 1997Dallas, Tx, UsDeveloped and implemented common test solutions/standards for ASICs, CCAs, and subsystems.
Greg Young Skills
Greg Young Education Details
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Southern Methodist UniversityBachelor Of Science
Frequently Asked Questions about Greg Young
What company does Greg Young work for?
Greg Young works for Best Robotics, Inc
What is Greg Young's role at the current company?
Greg Young's current role is Director of Operations.
What is Greg Young's email address?
Greg Young's email address is gr****@****amd.com
What is Greg Young's direct phone number?
Greg Young's direct phone number is +151294*****
What schools did Greg Young attend?
Greg Young attended Southern Methodist University.
What skills is Greg Young known for?
Greg Young has skills like Asic, Dft, Soc, Semiconductors, Ic, Embedded Systems, Testing, Verilog, Atpg, Low Power Design, Processors, Boundary Scan.
Who are Greg Young's colleagues?
Greg Young's colleagues are Syed Uzair Ali, Cyril Laurie, Ashlesha A., Laura Marin, Phaik Hoon Ong, Nandula Sasank, Dostonbek Mirzahamdamov.
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